Daten werden geladen obwohl sw(0) nicht betätigt wurde für we.

[peter (Gast)]

Hallo, ich habe eine RAM-Compenente gebastelt.
Die Datenübergabe findet sofort statt, nachdem ich es in den DE1 geladen 
habe, ohne den Schiebeschalter SW(0) zu betätigen.

Woran liegt das bitte ?

Danke.

Gruss

Diese VHDL bindet die Sync_ram.vhdl ein:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity c_sync_ram is port(
  clock : in  std_logic;
  led_g : out STD_LOGIC_VECTOR(7 downto 0);
  sw    : in  STD_LOGIC_VECTOR(0 downto 0)
  ); 
end c_sync_ram; 
            
architecture Behavioral of c_sync_ram is

signal we      : STD_LOGIC;
signal address : std_logic_vector (7 downto 0);
signal datain  :   std_logic_vector (7 downto 0);
signal dataout :  std_logic_vector (7 downto 0);
signal read_address :  std_logic_vector(7 downto 0);

component sync_ram port(
  we      : in STD_LOGIC; 
  address : in std_logic_vector (7 downto 0);
  datain  : in std_logic_vector (7 downto 0);
  dataout : inout std_logic_vector (7 downto 0);
  clock   : in  std_logic;
  read_address : in std_logic_vector(7 downto 0)
 );
end component;

begin
io1 : sync_ram  port map(we,address,datain,dataout,clock,read_address);

process(clock)
begin
  if rising_edge(clock) then
    if sw(0)='1' then
      we <='1';
      address<="00001111";
      datain<="11000011";
    else
      we<='0'; 
      read_address<="00001111";       
    end if;    
  end if;
end process;  

led_g<=dataout;

end Behavioral;

sync_ram:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;

entity sync_ram is
  port (
    clock   : in  std_logic;
    we      : in  std_logic;
    address : in  std_logic_vector (7 downto 0);
    datain  : in  std_logic_vector (7 downto 0);
    dataout : out std_logic_vector (7 downto 0);
    read_address : in std_logic_vector(7 downto 0)
  );
end entity sync_ram;

architecture RTL of sync_ram is

  type ram_type is array (0 to 255) of std_logic_vector(datain'range);
  signal ram : ram_type;
  
begin

process(clock) is
begin
    if rising_edge(clock) then
      if we = '1' then
        ram(to_integer(unsigned(address))) <= datain;
      else
        dataout <= ram(to_integer(unsigned(read_address)));
      end if;  
    end if;
end process;

end architecture RTL;

[peter (Gast)]

Wenn der Wert nicht der richtigen Adresse entspricht 
:read_address<="00001111"
werden auch keine Daten angezeigt. Das RAM funktioniert also mit den 
Adressen.

Gruss

[Matthias (Gast)]

Vll ist der sw low aktiv...

[peter (Gast)]

JUp, danke.

Habe ein neues RAM erstellt.

Gruss