1 | Library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_arith.all;
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4 | use ieee.std_logic_unsigned.all;
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5 |
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6 | entity Bubblesort is
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7 | end Bubblesort;
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8 |
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9 | architecture Behavioral of Bubblesort is
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10 |
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11 | -- Signals RAM
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12 | signal addra : std_logic_vector(5 downto 0) := (others => '0');
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13 | signal addrb : std_logic_vector(5 downto 0) := (others => '0');
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14 | signal addrb_d1 : std_logic_vector(5 downto 0) := (others => '0');
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15 | signal addrb_d2 : std_logic_vector(5 downto 0) := (others => '0');
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16 | signal addrb_d3 : std_logic_vector(5 downto 0) := (others => '0');
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17 | signal addrb_d4 : std_logic_vector(5 downto 0) := (others => '0');
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18 | signal dout_a : std_logic_vector(15 downto 0) := (others => '0');
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19 | signal din_a : std_logic_vector(15 downto 0) := (others => '0');
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20 | signal din_b : std_logic_vector(15 downto 0) := (others => '0');
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21 | signal we_a : std_logic_vector(0 downto 0) := (others => '0');
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22 | signal we_b : std_logic_vector(0 downto 0) := (others => '0');
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23 |
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24 | -- Signals Bubble
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25 | signal busy : std_logic := '0';
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26 | signal value1 : std_logic_vector(15 downto 0) := (others => '0');
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27 | signal value2 : std_logic_vector(15 downto 0) := (others => '0');
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28 | signal temp : std_logic_vector(15 downto 0) := (others => '0');
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29 | signal n : integer range 0 to 64;
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30 | signal start : std_logic := '0';
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31 | signal clk : std_logic := '0';
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32 | signal enable : std_logic := '0';
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33 | signal done : std_logic := '0';
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34 | signal reset : std_logic := '0';
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35 | signal reset_count : std_logic_vector(1 downto 0) := (others => '0');
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36 | signal i : std_logic_vector(5 downto 0) := (others => '0');
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37 |
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38 |
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39 | begin
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40 |
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41 |
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42 | -------------------------------------------------------------------
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43 | -- TESTBENCH
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44 | -------------------------------------------------------------------
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45 | clk <= not clk after 20 ns; -- 25 MHz Taktfrequenz
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46 | enable <= '1';
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47 | start <= '1';
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48 |
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49 | -------------------------------------------------------------------
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50 | -- INSTANTIATE BUBBLE_RAM
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51 | -------------------------------------------------------------------
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52 | BUBBLE : entity work.BUBBLE
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53 | port map
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54 | (
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55 | clka => clk,
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56 | wea => "0",
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57 | addra => i,
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58 | dina => din_a,
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59 | douta => value2,
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60 | clkb => clk,
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61 | web => we_b,
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62 | addrb => addrb_d4,
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63 | dinb => din_b,
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64 | doutb => open
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65 | );
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66 |
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67 | -------------------------------------------------------------------
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68 | -- DELAYS
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69 | -------------------------------------------------------------------
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70 | p_del: process(clk) is
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71 | begin
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72 | if rising_edge(clk) then
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73 | value1 <= value2;
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74 | end if;
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75 | end process;
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76 |
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77 | p_adrb_del1: process(clk) is
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78 | begin
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79 | if rising_edge(clk) then
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80 | addrb_d1 <= addrb;
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81 | end if;
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82 | end process;
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83 |
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84 | p_adrb_del2: process(clk) is
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85 | begin
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86 | if rising_edge(clk) then
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87 | addrb_d2 <= addrb_d1;
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88 | end if;
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89 | end process;
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90 |
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91 | p_adrb_del3: process(clk) is
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92 | begin
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93 | if rising_edge(clk) then
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94 | addrb_d3 <= addrb_d2;
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95 | end if;
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96 | end process;
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97 |
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98 |
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99 | p_adrb_del4: process(clk) is
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100 | begin
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101 | if rising_edge(clk) then
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102 | addrb_d4 <= addrb_d3;
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103 | end if;
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104 | end process;
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105 |
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106 | -------------------------------------------------------------------
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107 | -- GENERATE RESET
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108 | -------------------------------------------------------------------
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109 | p_reset_count: process(clk) is
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110 | begin
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111 | if rising_edge(clk) then
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112 | if (reset_count < "10") then
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113 | reset <= '1';
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114 | reset_count <= reset_count + 1;
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115 | else
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116 | reset <= '0';
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117 | reset_count <= "11";
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118 | end if;
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119 | end if;
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120 | end process;
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121 |
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122 | -------------------------------------------------------------------
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123 | -- BUBBLE ALGORITHM
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124 | -------------------------------------------------------------------
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125 | p_bubble: process(clk) is
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126 | begin
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127 | if rising_edge(clk) then
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128 | if (busy = '0') then
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129 | if (start = '1') then
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130 | busy <= '1';
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131 | n <= 0;
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132 | i <= "000000";
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133 | end if;
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134 | else
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135 | if (n < 64) then
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136 | if (i < "111111") then -- (n -1) = 63
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137 | if value1 > value2 then
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138 | TEMP <= value2;
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139 |
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140 | we_b <= "1";
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141 | addrb <= addra + 1;
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142 | din_b <= TEMP;
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143 | else
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144 | we_b <= "0";
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145 | addrb <= addra + 1;
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146 | end if;
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147 | i <= i+1; -- addra
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148 | else
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149 | i <= (others => '0');
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150 | n <= n + 1;
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151 | end if;
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152 | else
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153 | busy <= '0';
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154 | --do <= din;
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155 | end if;
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156 | end if;
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157 | end if;
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158 | end process;
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159 |
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160 | done <= '1' when start = '0' and busy = '0' else '0';
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161 |
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162 | end Behavioral;
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