1 | /*--------------------------------------------------------------------------
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2 |
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3 | Module Private Functions
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4 |
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5 | ---------------------------------------------------------------------------*/
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6 |
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7 | /* MMC/SD command (SPI mode) */
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8 | #define CMD0 (0) /* GO_IDLE_STATE */
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9 | #define CMD1 (1) /* SEND_OP_COND */
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10 | #define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */
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11 | #define CMD8 (8) /* SEND_IF_COND */
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12 | #define CMD9 (9) /* SEND_CSD */
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13 | #define CMD10 (10) /* SEND_CID */
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14 | #define CMD12 (12) /* STOP_TRANSMISSION */
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15 | #define CMD13 (13) /* SEND_STATUS */
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16 | #define ACMD13 (0x80+13) /* SD_STATUS (SDC) */
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17 | #define CMD16 (16) /* SET_BLOCKLEN */
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18 | #define CMD17 (17) /* READ_SINGLE_BLOCK */
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19 | #define CMD18 (18) /* READ_MULTIPLE_BLOCK */
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20 | #define CMD23 (23) /* SET_BLOCK_COUNT */
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21 | #define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */
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22 | #define CMD24 (24) /* WRITE_BLOCK */
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23 | #define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
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24 | #define CMD32 (32) /* ERASE_ER_BLK_START */
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25 | #define CMD33 (33) /* ERASE_ER_BLK_END */
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26 | #define CMD38 (38) /* ERASE */
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27 | #define CMD55 (55) /* APP_CMD */
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28 | #define CMD58 (58) /* READ_OCR */
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29 |
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30 |
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31 | static
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32 | DSTATUS Stat = STA_NOINIT; /* Disk status */
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33 |
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34 | static
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35 | BYTE CardType; /* b0:MMC, b1:SDv1, b2:SDv2, b3:Block addressing */
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36 |
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37 |
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38 |
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39 | /*-----------------------------------------------------------------------*/
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40 | /* Transmit bytes to the card (bitbanging) */
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41 | /*-----------------------------------------------------------------------*/
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42 |
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43 | static
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44 | void ICACHE_FLASH_ATTR xmit_mmc (
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45 | const BYTE* buff, /* Data to be sent */
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46 | UINT bc /* Number of bytes to send */
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47 | )
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48 | {
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49 | uart0_sendStr("global Debug: Transmit bytes to card \r\n");
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50 | BYTE d;
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51 |
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52 |
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53 | do {
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54 | d = *buff++; /* Get a byte to be sent */
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55 | if (d & 0x80)DI_H() ;else DI_L(); /* bit7 */
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56 | CK_H(); CK_L();
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57 | if (d & 0x40)DI_H() ;else DI_L(); /* bit6 */
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58 | CK_H(); CK_L();
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59 | if (d & 0x20) DI_H() ; else DI_L(); /* bit5 */
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60 | CK_H(); CK_L();
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61 | if (d & 0x10) DI_H() ;else DI_L(); /* bit4 */
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62 | CK_H(); CK_L();
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63 | if (d & 0x08) DI_H() ;else DI_L(); /* bit3 */
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64 | CK_H(); CK_L();
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65 | if (d & 0x04) DI_H(); else DI_L(); /* bit2 */
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66 | CK_H(); CK_L();
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67 | if (d & 0x02) DI_H(); else DI_L(); /* bit1 */
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68 | CK_H(); CK_L();
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69 | if (d & 0x01) DI_H(); else DI_L(); /* bit0 */
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70 | CK_H(); CK_L();
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71 | } while (--bc);
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72 | }
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73 |
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74 |
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75 |
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76 | /*-----------------------------------------------------------------------*/
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77 | /* Receive bytes from the card (bitbanging) */
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78 | /*-----------------------------------------------------------------------*/
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79 |
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80 | static
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81 | void ICACHE_FLASH_ATTR rcvr_mmc (
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82 | BYTE *buff, /* Pointer to read buffer */
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83 | UINT bc /* Number of bytes to receive */
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84 | )
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85 | {
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86 | BYTE r;
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87 |
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88 | uart0_sendStr("global Debug: Receive bytes from card \r\n");
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89 | DI_H(); /* Send 0xFF */
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90 |
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91 | do {
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92 | r = 0; if (DO) r++; /* bit7 */
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93 | CK_H(); CK_L();
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94 | r <<= 1; if (DO) r++; /* bit6 */
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95 | CK_H(); CK_L();
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96 | r <<= 1; if (DO) r++; /* bit5 */
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97 | CK_H(); CK_L();
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98 | r <<= 1; if (DO) r++; /* bit4 */
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99 | CK_H(); CK_L();
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100 | r <<= 1; if (DO) r++; /* bit3 */
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101 | CK_H(); CK_L();
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102 | r <<= 1; if (DO) r++; /* bit2 */
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103 | CK_H(); CK_L();
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104 | r <<= 1; if (DO) r++; /* bit1 */
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105 | CK_H(); CK_L();
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106 | r <<= 1; if (DO) r++; /* bit0 */
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107 | CK_H(); CK_L();
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108 | *buff++ = r; /* Store a received byte */
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109 | } while (--bc);
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110 | }
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111 |
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112 |
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113 |
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114 | /*-----------------------------------------------------------------------*/
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115 | /* Wait for card ready */
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116 | /*-----------------------------------------------------------------------*/
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117 |
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118 | static
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119 | int ICACHE_FLASH_ATTR wait_ready (void) /* 1:OK, 0:Timeout */
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120 | {
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121 | BYTE d;
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122 | UINT tmr;
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123 |
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124 | uart0_sendStr("global Debug: Wait for card ready \r\n");
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125 | for (tmr = 5000; tmr; tmr--) { /* Wait for ready in timeout of 500ms */
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126 | rcvr_mmc(&d, 1);
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127 | if (d == 0xFF) break;
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128 | dly_us(100);
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129 | }
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130 |
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131 | return tmr ? 1 : 0;
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132 | }
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133 |
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134 |
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135 |
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136 | /*-----------------------------------------------------------------------*/
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137 | /* Deselect the card and release SPI bus */
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138 | /*-----------------------------------------------------------------------*/
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139 |
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140 | static
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141 | void ICACHE_FLASH_ATTR deselect (void)
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142 | {
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143 | uart0_sendStr("global Debug: deselect bus free \r\n");
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144 | #ifdef DEBI
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145 | uart0_sendStr("Debug: deselect \r\n");
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146 | #endif
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147 | BYTE d;
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148 |
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149 | CS_H(); /* Set CS# high */
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150 | rcvr_mmc(&d, 1); /* Dummy clock (force DO hi-z for multiple slave SPI) */
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151 | }
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152 |
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153 |
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154 |
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155 | /*-----------------------------------------------------------------------*/
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156 | /* Select the card and wait for ready */
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157 | /*-----------------------------------------------------------------------*/
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158 |
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159 | static
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160 | int ICACHE_FLASH_ATTR select (void) /* 1:OK, 0:Timeout */
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161 | {
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162 | uart0_sendStr("Global Debug: select and wait for ready \r\n");
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163 | #ifdef DEBI
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164 | uart0_sendStr("Debug: select \r\n");
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165 | #endif
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166 |
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167 | BYTE d;
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168 |
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169 | CS_L(); /* Set CS# low */
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170 | rcvr_mmc(&d, 1); /* Dummy clock (force DO enabled) */
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171 | if (wait_ready()) return 1; /* Wait for card ready */
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172 |
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173 | deselect();
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174 | return 0; /* Failed */
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175 | }
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176 |
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177 |
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178 |
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179 | /*-----------------------------------------------------------------------*/
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180 | /* Receive a data packet from the card */
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181 | /*-----------------------------------------------------------------------*/
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182 |
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183 | static
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184 | int ICACHE_FLASH_ATTR rcvr_datablock ( /* 1:OK, 0:Failed */
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185 | BYTE *buff, /* Data buffer to store received data */
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186 | UINT btr /* Byte count */
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187 | )
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188 | {
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189 | BYTE d[2];
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190 | UINT tmr;
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191 |
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192 | uart0_sendStr("global Debug: Receive a data packet from card \r\n");
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193 | for (tmr = 1000; tmr; tmr--) { /* Wait for data packet in timeout of 100ms */
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194 | rcvr_mmc(d, 1);
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195 | if (d[0] != 0xFF) break;
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196 | dly_us(100);
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197 | }
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198 | if (d[0] != 0xFE) return 0; /* If not valid data token, return with error */
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199 |
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200 | rcvr_mmc(buff, btr); /* Receive the data block into buffer */
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201 | rcvr_mmc(d, 2); /* Discard CRC */
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202 |
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203 | return 1; /* Return with success */
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204 | }
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205 |
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206 |
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207 |
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208 | /*-----------------------------------------------------------------------*/
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209 | /* Send a data packet to the card */
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210 | /*-----------------------------------------------------------------------*/
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211 |
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212 | static
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213 | int ICACHE_FLASH_ATTR xmit_datablock ( /* 1:OK, 0:Failed */
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214 | const BYTE *buff, /* 512 byte data block to be transmitted */
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215 | BYTE token /* Data/Stop token */
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216 | )
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217 | {
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218 | uart0_sendStr("Debug: Send Data Packet to the Card \r\n");
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219 | BYTE d[2];
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220 |
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221 |
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222 | if (!wait_ready()) return 0;
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223 |
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224 | d[0] = token;
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225 | xmit_mmc(d, 1); /* Xmit a token */
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226 | if (token != 0xFD) { /* Is it data token? */
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227 | xmit_mmc(buff, 512); /* Xmit the 512 byte data block to MMC */
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228 | rcvr_mmc(d, 2); /* Xmit dummy CRC (0xFF,0xFF) */
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229 | rcvr_mmc(d, 1); /* Receive data response */
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230 | if ((d[0] & 0x1F) != 0x05) /* If not accepted, return with error */
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231 | return 0;
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232 | }
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233 |
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234 | return 1;
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235 | }
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236 |
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237 |
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238 |
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239 | /*-----------------------------------------------------------------------*/
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240 | /* Send a command packet to the card */
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241 | /*-----------------------------------------------------------------------*/
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242 |
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243 | static
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244 | BYTE ICACHE_FLASH_ATTR send_cmd ( /* Returns command response (bit7==1:Send failed)*/
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245 | BYTE cmd, /* Command byte */
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246 | DWORD arg /* Argument */
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247 | )
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248 | {
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249 | if ((GPIO_INPUT_GET(13) & 0x01)) uart0_sendStr("MISO: TRUE(1)\r\n"); else uart0_sendStr("MISO: FALSE(0)\r\n");
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250 |
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251 | uart0_sendStr("Debug: Send Command Packet to the card \r\n");
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252 | BYTE n, d, buf[6];
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253 |
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254 |
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255 | if (cmd & 0x80) { /* ACMD<n> is the command sequense of CMD55-CMD<n> */
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256 | cmd &= 0x7F;
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257 | n = send_cmd(CMD55, 0);
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258 | if (n > 1) return n;
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259 | }
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260 |
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261 | /* Select the card and wait for ready except to stop multiple block read */
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262 | if (cmd != CMD12) {
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263 | deselect();
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264 | if (!select()) return 0xFF;
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265 | }
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266 |
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267 | /* Send a command packet */
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268 | buf[0] = 0x40 | cmd; /* Start + Command index */
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269 | buf[1] = (BYTE)(arg >> 24); /* Argument[31..24] */
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270 | buf[2] = (BYTE)(arg >> 16); /* Argument[23..16] */
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271 | buf[3] = (BYTE)(arg >> 8); /* Argument[15..8] */
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272 | buf[4] = (BYTE)arg; /* Argument[7..0] */
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273 | n = 0x01; /* Dummy CRC + Stop */
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274 | if (cmd == CMD0) n = 0x95; /* (valid CRC for CMD0(0)) */
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275 | if (cmd == CMD8) n = 0x87; /* (valid CRC for CMD8(0x1AA)) */
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276 | buf[5] = n;
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277 | xmit_mmc(buf, 6);
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278 |
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279 | /* Receive command response */
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280 | if (cmd == CMD12) rcvr_mmc(&d, 1); /* Skip a stuff byte when stop reading */
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281 | n = 10; /* Wait for a valid response in timeout of 10 attempts */
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282 | do
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283 | rcvr_mmc(&d, 1);
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284 | while ((d & 0x80) && --n);
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285 |
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286 | return d; /* Return with the response value */
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287 | }
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288 |
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289 |
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290 |
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291 | /*--------------------------------------------------------------------------
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292 |
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293 | Public Functions
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294 |
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295 | ---------------------------------------------------------------------------*/
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296 |
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297 |
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298 | /*-----------------------------------------------------------------------*/
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299 | /* Get Disk Status */
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300 | /*-----------------------------------------------------------------------*/
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301 |
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302 | DSTATUS ICACHE_FLASH_ATTR disk_status (
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303 | BYTE drv /* Drive number (always 0) */
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304 | )
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305 | {
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306 | if (drv) return STA_NOINIT;
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307 |
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308 | return Stat;
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309 | }
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310 |
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311 |
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312 |
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313 | /*-----------------------------------------------------------------------*/
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314 | /* Initialize Disk Drive */
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315 | /*-----------------------------------------------------------------------*/
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316 |
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317 | DSTATUS ICACHE_FLASH_ATTR disk_initialize (
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318 | BYTE drv /* Physical drive nmuber (0) */
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319 | )
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320 | {
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321 | uart0_sendStr("Debug: disk init \r\n");
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322 | BYTE n, ty, cmd, buf[4];
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323 | UINT tmr;
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324 | DSTATUS s;
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325 |
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326 |
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327 | if (drv) return RES_NOTRDY;
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328 | uart0_sendStr("Debug: disk init delay 1 \r\n");
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329 |
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330 | // 1 * 1000 * 1000 = 1 sec
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331 | // 1 * 1000 = 1 ms
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332 | // 1 = 1 us
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333 |
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334 | // dly_us(10000); /* 10ms */
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335 | os_delay_us(10 * 1000);
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336 |
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337 | uart0_sendStr("Debug: disk init delay 2 \r\n");
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338 | CS_INIT(); CS_H(); /* Initialize port pin tied to CS */
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339 | uart0_sendStr("Debug: CS init done \r\n");
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340 | CK_INIT(); CK_L(); /* Initialize port pin tied to SCLK */
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341 | uart0_sendStr("Debug: CK init done \r\n");
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342 | DI_INIT(); /* Initialize port pin tied to DI */
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343 | uart0_sendStr("Debug: DI init done \r\n");
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344 | DO_INIT(); /* Initialize port pin tied to DO */
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345 | uart0_sendStr("Debug: DO init done \r\n");
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346 | uint8_t ccc[2]={0};
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347 | uart0_sendStr("Debug: Try 80 dummy clocks ..\r\n");
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348 | for (n = 10; n ; n--) {
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349 | os_sprintf(ccc,"%i\r\n",n);
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350 | uart0_sendStr(">: ");
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351 | uart0_sendStr(ccc);
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352 | rcvr_mmc(buf, 1); /* Apply 80 dummy clocks and the card gets ready to receive command */
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353 | }
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354 |
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355 | // for (n = 10; n; n--) rcvr_mmc(buf, 1); /* Apply 80 dummy clocks and the card gets ready to receive command */
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356 |
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357 | uart0_sendStr("Debug: 80 dummy clocks done\r\n");
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358 |
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359 | ty = 0;
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360 | if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */
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361 | uart0_sendStr("global Debug: IDLE OK\r\n");
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362 | if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */
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363 | rcvr_mmc(buf, 4); /* Get trailing return value of R7 resp */
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364 | if (buf[2] == 0x01 && buf[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */
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365 | uart0_sendStr("global Debug: Card works 2.7 - 3.6 V \r\n");
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366 | for (tmr = 1000; tmr; tmr--) { /* Wait for leaving idle state (ACMD41 with HCS bit) */
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367 | if (send_cmd(ACMD41, 1UL << 30) == 0) break;
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368 | dly_us(1000);
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369 | }
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370 | if (tmr && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */
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371 | rcvr_mmc(buf, 4);
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372 | ty = (buf[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* SDv2 */
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373 | }
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374 | }
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375 | } else { /* SDv1 or MMCv3 */
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376 | if (send_cmd(ACMD41, 0) <= 1) {
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377 | ty = CT_SD1; cmd = ACMD41; /* SDv1 */
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378 | } else {
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379 | ty = CT_MMC; cmd = CMD1; /* MMCv3 */
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380 | }
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381 | for (tmr = 1000; tmr; tmr--) { /* Wait for leaving idle state */
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382 | if (send_cmd(cmd, 0) == 0) break;
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383 | dly_us(1000);
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384 | }
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385 | if (!tmr || send_cmd(CMD16, 512) != 0) /* Set R/W block length to 512 */
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386 | ty = 0;
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387 | }
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388 | }
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389 | CardType = ty;
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390 | s = ty ? 0 : STA_NOINIT;
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391 | Stat = s;
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392 |
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393 | deselect();
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394 |
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395 | return s;
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396 | }
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397 |
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398 |
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399 |
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400 | /*-----------------------------------------------------------------------*/
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401 | /* Read Sector(s) */
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402 | /*-----------------------------------------------------------------------*/
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403 |
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404 | DRESULT ICACHE_FLASH_ATTR disk_read (
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405 | BYTE drv, /* Physical drive nmuber (0) */
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406 | BYTE *buff, /* Pointer to the data buffer to store read data */
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407 | DWORD sector, /* Start sector number (LBA) */
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408 | UINT count /* Sector count (1..128) */
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409 | )
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410 | {
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411 | uart0_sendStr("Debug: Disk read \r\n");
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412 | BYTE cmd;
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413 |
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414 |
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415 | if (disk_status(drv) & STA_NOINIT) return RES_NOTRDY;
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416 | if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert LBA to byte address if needed */
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417 |
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418 | cmd = count > 1 ? CMD18 : CMD17; /* READ_MULTIPLE_BLOCK : READ_SINGLE_BLOCK */
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419 | if (send_cmd(cmd, sector) == 0) {
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420 | do {
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421 | if (!rcvr_datablock(buff, 512)) break;
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422 | buff += 512;
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423 | } while (--count);
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424 | if (cmd == CMD18) send_cmd(CMD12, 0); /* STOP_TRANSMISSION */
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425 | }
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426 | deselect();
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427 |
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428 | return count ? RES_ERROR : RES_OK;
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429 | }
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430 |
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431 |
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432 |
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433 | /*-----------------------------------------------------------------------*/
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434 | /* Write Sector(s) */
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435 | /*-----------------------------------------------------------------------*/
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436 |
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437 | DRESULT ICACHE_FLASH_ATTR disk_write (
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438 | BYTE drv, /* Physical drive nmuber (0) */
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439 | const BYTE *buff, /* Pointer to the data to be written */
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440 | DWORD sector, /* Start sector number (LBA) */
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441 | UINT count /* Sector count (1..128) */
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442 | )
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443 | {
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444 | uart0_sendStr("Debug: Disk Write \r\n");
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445 | if (disk_status(drv) & STA_NOINIT) return RES_NOTRDY;
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446 | if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert LBA to byte address if needed */
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447 |
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448 | if (count == 1) { /* Single block write */
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449 | if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */
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450 | && xmit_datablock(buff, 0xFE))
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451 | count = 0;
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452 | }
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453 | else { /* Multiple block write */
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454 | if (CardType & CT_SDC) send_cmd(ACMD23, count);
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455 | if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */
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456 | do {
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457 | if (!xmit_datablock(buff, 0xFC)) break;
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458 | buff += 512;
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459 | } while (--count);
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460 | if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */
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461 | count = 1;
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462 | }
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463 | }
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464 | deselect();
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465 |
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466 | return count ? RES_ERROR : RES_OK;
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467 | }
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468 |
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469 |
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470 | /*-----------------------------------------------------------------------*/
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471 | /* Miscellaneous Functions */
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472 | /*-----------------------------------------------------------------------*/
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473 |
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474 | DRESULT ICACHE_FLASH_ATTR disk_ioctl (
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475 | BYTE drv, /* Physical drive nmuber (0) */
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476 | BYTE ctrl, /* Control code */
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477 | void *buff /* Buffer to send/receive control data */
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478 | )
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479 | {
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480 | DRESULT res;
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481 | BYTE n, csd[16];
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482 | DWORD cs;
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483 |
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484 |
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485 | if (disk_status(drv) & STA_NOINIT) return RES_NOTRDY; /* Check if card is in the socket */
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486 |
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487 | res = RES_ERROR;
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488 | switch (ctrl) {
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489 | case CTRL_SYNC : /* Make sure that no pending write process */
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490 | if (select()) res = RES_OK;
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491 | break;
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492 |
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493 | case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
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494 | if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) {
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495 | if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */
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496 | cs = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1;
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497 | *(DWORD*)buff = cs << 10;
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498 | } else { /* SDC ver 1.XX or MMC */
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499 | n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
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500 | cs = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1;
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501 | *(DWORD*)buff = cs << (n - 9);
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502 | }
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503 | res = RES_OK;
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504 | }
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505 | break;
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506 |
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507 | case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */
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508 | *(DWORD*)buff = 128;
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509 | res = RES_OK;
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510 | break;
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511 |
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512 | default:
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513 | res = RES_PARERR;
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514 | }
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515 |
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516 | deselect();
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517 |
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518 | return res;
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519 | }
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