1 | /* _ _ _ _ _ _ _ _ _ _
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2 | * /\ \ /\ \ /\ \ /\_\ / /\ /\ \ /\ \ /\_\/\_\ _ /\ \
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3 | * / \ \ \_\ \ / \ \ / / / _ / / \ \_\ \ / \ \ / / / / //\_\ / \ \
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4 | * / /\ \ \ /\__ \ / /\ \ \ \ \ \__ /\_\ / / /\ \__ /\__ \ / /\ \ \ /\ \/ \ \/ / /__/ /\ \ \
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5 | * / / /\ \_\ / /_ \ \ / / /\ \ \ \ \___\ / / // / /\ \___\ / /_ \ \ / / /\ \ \ / \____\__/ //___/ /\ \ \
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6 | * / / /_/ / / / / /\ \ \ / / / \ \_\ \__ / / / / \ \ \ \/___// / /\ \ \ / / / \ \_\ / /\/________/ \___\/ / / /
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7 | * / / /__\/ / / / / \/_// / / \/_/ / / / / / / \ \ \ / / / \/_// / / / / // / /\/_// / / / / /
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8 | * / / /_____/ / / / / / / / / / / / /_ \ \ \ / / / / / / / / // / / / / / / / / _
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9 | * / / /\ \ \ / / / / / /________ / / /___/ / //_/\__/ / / / / / / / /___/ / // / / / / / \ \ \__/\_\
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10 | * / / / \ \ \/_/ / / / /_________\/ / /____\/ / \ \/___/ / /_/ / / / /____\/ / \/_/ / / / \ \___\/ /
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11 | * \/_/ \_\/\_\/ \/____________/\/_________/ \_____\/ \_\/ \/_________/ \/_/ \/___/_/
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12 | *
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13 | *
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14 | * DMX Receiver for ATxMega
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15 | * Tested with ATxMega256A3U
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16 | * Uses external 16 MHz oscillator together with internal PLL to generate 32MHz system clock
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17 | *
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18 | *
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19 | *
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20 | * Released under the "Don't care" license
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21 | * Feel free to use this code in any way you want
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22 | * Also no support will be given in any way
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23 | *
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24 | * Code V1.0
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25 | * 25.09.2015
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26 | */
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27 |
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28 | #include <avr/io.h>
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29 | #include <stdio.h>
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30 | #include <avr/interrupt.h>
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31 |
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32 | //Buffer to store the DMX stream (start code + 512 channels)
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33 | volatile unsigned int dmx_buffer[513];
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34 |
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35 | void Clock_init(void){
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36 | //Xosc Bit 7&6 to 11 | Bit 3 to 0 as 1011
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37 | OSC.XOSCCTRL = OSC_FRQRANGE_12TO16_gc | OSC_XOSCSEL_XTAL_16KCLK_gc;
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38 | //Bit 3 to 1 to enable external oscillator
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39 | OSC.CTRL |= OSC_XOSCEN_bm;
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40 | //wait for stable clock
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41 | while(!(OSC.STATUS & OSC_XOSCRDY_bm));
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42 | //Disable register protection for 4 clocks
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43 | CCP = CCP_IOREG_gc;
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44 | //Set Bit 2:0 to 011 for external oscillator
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45 | CLK.CTRL = CLK_SCLKSEL_XOSC_gc;
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46 | }
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47 |
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48 | void PLL_init(void){
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49 | //Bit 7:0 to 11 for external oscillator as PLL source | 2 as multiplication value
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50 | OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | 0x02;
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51 | //enable PLL
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52 | OSC.CTRL |= OSC_PLLEN_bm;
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53 | //wait for stable oscillation
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54 | while (!(OSC.STATUS & OSC_PLLRDY_bm));
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55 | //Disable register protection for 4 clocks
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56 | CCP = CCP_IOREG_gc;
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57 | //Set Bit 2:0 for PLL as clock source
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58 | CLK.CTRL = CLK_SCLKSEL_PLL_gc;
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59 | }
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60 |
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61 | void UART_init(void){
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62 | // Pin from USARTC0 TxD C3 set to input
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63 | PORTC.DIRCLR = PIN6_bm;
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64 | // Asynchronous Modus
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65 | USARTC1.CTRLC = (USARTC0.CTRLC & ~USART_CMODE_gm ) | USART_CMODE_ASYNCHRONOUS_gc;
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66 | // No parity
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67 | USARTC1.CTRLC = (USARTC0.CTRLC & ~USART_PMODE_gm ) | USART_PMODE_DISABLED_gc;
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68 | // 8 data bits
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69 | USARTC1.CTRLC = (USARTC0.CTRLC & ~USART_CHSIZE_gm ) | USART_CHSIZE_8BIT_gc;
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70 | // 2 stop bits
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71 | USARTC1.CTRLC = (USARTC0.CTRLC & ~USART_SBMODE_bm) | (0x01<<3);
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72 | // 250 kBaud
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73 | USARTC1.BAUDCTRLA = 07;
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74 | // 250 kBaud
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75 | USARTC1.BAUDCTRLB =(0 << USART_BSCALE0_bp)|(07 >> 8);
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76 | // Set interrupt level of RX Int to low
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77 | USARTC1.CTRLA = (USARTC1.CTRLA & ~USART_RXCINTLVL_gm) | USART_RXCINTLVL_LO_gc;
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78 | // activate USARTC1
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79 | USARTC1.CTRLB = USART_RXEN_bm;
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80 |
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81 | }
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82 |
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83 | int main (void){
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84 |
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85 | //Start-Up external crystal
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86 | Clock_init();
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87 | //Use PLL to generate 32 MHz tact from external crystal
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88 | PLL_init();
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89 | //Init UART
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90 | UART_init();
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91 |
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92 | /* Enable LO interrupt level. */
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93 | PMIC.CTRL |= PMIC_LOLVLEN_bm;
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94 | //Global Interrupts Enable
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95 | sei();
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96 |
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97 | while (1)
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98 | {
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99 | }
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100 |
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101 | return 0;
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102 | }
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103 |
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104 | //Interupt vector for USART C1 RX complete
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105 | ISR (USARTC1_RXC_vect){
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106 | //Let's count the dmx channels
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107 | static unsigned int dmx_channel_rx_count = 0;
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108 | //And check if dmx is valid
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109 | static unsigned char dmx_valid = 0;
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110 | //Tmp is never wrong
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111 | unsigned char tmp = 0;
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112 |
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113 | //Store currently received byte into tmp variable
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114 | tmp = USARTC1.DATA;
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115 |
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116 | //Check for framing error as start of dmx transmission
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117 | if(USARTC1.STATUS & USART_FERR_bm)
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118 | {
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119 | //Start to count at first channel
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120 | dmx_channel_rx_count = 0;
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121 | //Copy tmp into our dmx buffer at position 0
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122 | dmx_buffer[0] = tmp;
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123 | //now check if this value was a 0 which is the start code for normal dmx transmissions
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124 | if(dmx_buffer[0] == 0)
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125 | {
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126 | //ok dmx was valid
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127 | dmx_valid = 1;
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128 | //increase count to first dmx channel containing information
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129 | dmx_channel_rx_count++;
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130 | }
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131 | else
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132 | {
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133 | //sorry but first byte was not a dmx start code, let's wait for the next frame error
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134 | dmx_valid = 0;
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135 | }
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136 | return;
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137 | }
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138 |
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139 | //yippy dmx was valid so we can process the other 512 channels
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140 | if(dmx_valid)
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141 | {
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142 | //copy the received channel byte into the correct position of our dmx reception buffer
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143 | dmx_buffer[dmx_channel_rx_count] = tmp;
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144 | //repeat until we have gathered all 512 channels
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145 | if(dmx_channel_rx_count < 513)
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146 | {
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147 | dmx_channel_rx_count++;
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148 | }
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149 | return;
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150 | }
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151 | }
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