Mischung

Johnsn wrote:
> Leg dir am besten Lookup-Tables für Sinus/Cosinus an und verwende den
> Signed-Datentyp aus dem numeric_std Package für die Multiplikation.
>
> Ansonsten würde ich vorschlagen, dein Vorhaben genauer zu spezifizieren
> (welches FPGA, Bitbreite der Daten, geforderte Geschwindigkeit ...),
> dann kann dir besser geholfen werden!

Hallo Johnsn

wie kann ich eine Lookup-Tables für Sinus/Cosinus programmieren . ich 
habe schon eine synthese von Sinus/Cosinus mit der Cordic programmiert

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY cos_sin_core IS
  port (
  phase_in: IN std_logic_VECTOR(15 downto 0);
  x_out: OUT std_logic_VECTOR(15 downto 0);
  y_out: OUT std_logic_VECTOR(15 downto 0);
  rdy: OUT std_logic;
  clk: IN std_logic;
  ce: IN std_logic;
  aclr: IN std_logic;
  sclr: IN std_logic);
END cos_sin_core;

ARCHITECTURE cos_sin_core_a OF cos_sin_core IS
-- synthesis translate_off
component wrapped_cos_sin_core
  port (
  phase_in: IN std_logic_VECTOR(15 downto 0);
  x_out: OUT std_logic_VECTOR(15 downto 0);
  y_out: OUT std_logic_VECTOR(15 downto 0);
  rdy: OUT std_logic;
  clk: IN std_logic;
  ce: IN std_logic;
  aclr: IN std_logic;
  sclr: IN std_logic);
end component;

-- Configuration specification
  for all : wrapped_cos_sin_core use entity 
XilinxCoreLib.cordic_v3_0(behavioral)
    generic map(
      c_has_clk => 1,
      c_has_x_out => 1,
      c_has_y_in => 0,
      c_reg_inputs => 1,
      c_architecture => 2,
      c_input_width => 16,
      c_iterations => 3,
      c_precision => 16,
      c_has_rdy => 1,
      c_has_sclr => 1,
      c_has_nd => 0,
      c_scale_comp => 0,
      c_enable_rlocs => 1,
      c_has_phase_in => 1,
      c_has_rfd => 0,
      c_cordic_function => 2,
      c_has_ce => 1,
      c_mif_file_prefix => "cor1",
      c_round_mode => 3,
      c_has_aclr => 1,
      c_sync_enable => 1,
      c_has_y_out => 1,
      c_data_format => 0,
      c_reg_outputs => 1,
      c_coarse_rotate => 1,
      c_phase_format => 0,
      c_has_phase_out => 0,
      c_has_x_in => 0,
      c_pipeline_mode => -2,
      c_output_width => 16);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cos_sin_core
    port map (
      phase_in => phase_in,
      x_out => x_out,
      y_out => y_out,
      rdy => rdy,
      clk => clk,
      ce => ce,
      aclr => aclr,
      sclr => sclr);
-- synthesis translate_on

END cos_sin_core_a;