hallo liebe User ich bin neue Anfänger mit VHDL ich habe ein Projekt mit einen FPGA Xillinx Spartan3 da habe ich 86 PINs Frei mit ISE 8.1 versuche ich wie ich das auch in der Realität steuern muss die Eingänge und die Ausgänge mit VHDL zu stellen ich brauche 35 Inputs und 6 Outputs wenn ich die Entity mit VHDL deklariere und diese Eingänge und Ausgänge innerhalb dieser Entity deklariere dann bekomme ich eine Meldung: No design units detected in file. wie kann ich das lösen ich brauche doch insgesamt 35 Inputs und 6 Outputs ? danke
Gast
#657101
Zeigt dein code
vm wrote:
> Zeigt dein code
entity Test-Board is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
D0_IC1 : in STD_LOGIC;
D1_IC1 : in STD_LOGIC;
D2_IC1 : in STD_LOGIC;
D0_IC2 : in STD_LOGIC;
D1_IC2 : in STD_LOGIC;
D2_IC2 : in STD_LOGIC;
D0_IC3 : in STD_LOGIC;
D1_IC3 : in STD_LOGIC;
D2_IC3 : in STD_LOGIC;
D0_IC4 : in STD_LOGIC;
D1_IC4 : in STD_LOGIC;
D2_IC4 : in STD_LOGIC;
D0_IC5 : in STD_LOGIC;
D1_IC5 : in STD_LOGIC;
D2_IC5 : in STD_LOGIC;
D0_IC6 : in STD_LOGIC;
D1_IC6 : in STD_LOGIC;
D2_IC6 : in STD_LOGIC;
N1 : in STD_LOGIC;
N2 : in STD_LOGIC;
N3 : in STD_LOGIC;
N4 : in STD_LOGIC;
N5 : in STD_LOGIC;
N6 : in STD_LOGIC;
D3 : in STD_LOGIC;
D4 : in STD_LOGIC;
D5 : in STD_LOGIC;
D6 : in STD_LOGIC;
D7 : in STD_LOGIC;
D8 : in STD_LOGIC;
COM1 : out STD_LOGIC;
COM2 : out STD_LOGIC;
COM3 : out STD_LOGIC;
COM4 : out STD_LOGIC;
COM5 : out STD_LOGIC;
COM6 : out STD_LOGIC);
end Test-Board;
architecture Structure of Test-Board is
--Include Components
component IC
port( A0 : in STD_LOGIC;
A1 : in STD_LOGIC;
A2 : in STD_LOGIC;
EN : in STD_LOGIC;
N01 : in STD_LOGIC;
N02 : in STD_LOGIC;
N03 : in STD_LOGIC;
N04 : in STD_LOGIC;
N05 : in STD_LOGIC;
N06 : in STD_LOGIC;
COM : out STD_LOGIC
);
end component IC;
begin
--Instantiate Components
IC1 : IC
port map (
A0 => D0_IC1,
A1 => D1_IC1,
A2 => D2_IC1,
EN => D8,
N01 => N1,
N02 => N2,
N03 => N3,
N04 => N4,
N05 => N5,
N06 => N6,
COM => COM1
);
IC2 : IC
port map (
A0 => D0_IC2,
A1 => D1_IC2,
A2 => D2_IC2,
EN => D7,
N01 => N1,
N02 => N2,
N03 => N3,
N04 => N4,
N05 => N5,
N06 => N6,
COM => COM2
);
IC3 : IC
port map (
A0 => D0_IC3,
A1 => D1_IC3,
A2 => D2_IC3,
EN => D6,
N01 => N1,
N02 => N2,
N03 => N3,
N04 => N4,
N05 => N5,
N06 => N6,
COM => COM3
);
IC4 : IC
port map (
A0 => D0_IC4,
A1 => D1_IC4,
A2 => D2_IC4,
EN => D5,
N01 => N1,
N02 => N2,
N03 => N3,
N04 => N4,
N05 => N5,
N06 => N6,
COM => COM4
);
IC5 : IC
port map (
A0 => D0_IC5,
A1 => D1_IC5,
A2 => D2_IC5,
EN => D4,
N01 => N1,
N02 => N2,
N03 => N3,
N04 => N4,
N05 => N5,
N06 => N6,
COM => COM2
);
IC6 : IC
port map (
A0 => D0_IC6,
A1 => D1_IC6,
A2 => D2_IC6,
EN => D3,
N01 => N1,
N02 => N2,
N03 => N3,
N04 => N4,
N05 => N5,
N06 => N6,
COM => COM1
);
end architecture Test-Board;
"-" ist in Bezeichnern nicht erlaubt.
merciiiiiiiiiiiiiiiiiiiiiiiiii ganz lieben Dank es war genau das mein Problem
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