Ich bins schon wieder g, kann mir jemand sagen warum dieser code:
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | |
4 | entity QuadDecoder is |
5 | Port ( CLK : in std_logic; |
6 | A : in std_logic; |
7 | B : in std_logic; |
8 | RST : in std_logic; |
9 | UP_DOWN : out std_logic; |
10 | C_ENABLE : out std_logic; |
11 | ERR : out std_logic); |
12 | end QuadDecoder; |
13 | |
14 | architecture VERH of QuadDecoder is |
15 | |
16 | signal RST_SIG,A_OLD, B_OLD: std_logic; |
17 | |
18 | begin
|
19 | |
20 | QDecoder: process(CLK, RST, A, B) |
21 | variable DecPattern: std_logic_vector(3 downto 0); |
22 | begin
|
23 | if RST = '1' then |
24 | C_ENABLE <= '0'; |
25 | UP_DOWN <= '0'; |
26 | ERR <= '0'; |
27 | A_OLD <= '0'; |
28 | B_OLD <= '0'; |
29 | RST_SIG <= '1'; |
30 | |
31 | elsif CLK = '1' and CLK'event then |
32 | if RST_SIG = '1' and A = '0' and B = '0' then |
33 | RST_SIG <= '0'; |
34 | end if; |
35 | |
36 | if RST_SIG = '0' then |
37 | DecPattern := A & B & A_OLD & B_OLD; |
38 | A_OLD <= A; |
39 | B_OLD <= B; |
40 | |
41 | case DecPattern is |
42 | when "0000" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0'; |
43 | when "0001" => UP_DOWN <= '1'; C_ENABLE <= '1'; ERR <= '0'; |
44 | when "0010" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0'; |
45 | when "0011" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '1'; |
46 | when "0100" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0'; |
47 | when "0101" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0'; |
48 | when "0110" => UP_DOWN <= '1'; C_ENABLE <= '0'; ERR <= '1'; |
49 | when "0111" => UP_DOWN <= '1'; C_ENABLE <= '1'; ERR <= '0'; |
50 | when "1000" => UP_DOWN <= '1'; C_ENABLE <= '1'; ERR <= '0'; |
51 | when "1001" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '1'; |
52 | when "1010" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0'; |
53 | when "1011" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0'; |
54 | when "1100" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '1'; |
55 | when "1101" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0'; |
56 | when "1110" => UP_DOWN <= '1'; C_ENABLE <= '1'; ERR <= '0'; |
57 | when "1111" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0'; |
58 | when others => null; |
59 | end case; |
60 | end if; |
61 | end if; |
62 | end process QDecoder; |
63 | |
64 | end VERH; |
nicht korrekt synthetisiert wird ? Verhaltenssimulation und Post Fit Simulation weichen voneinander ab -> Siehe Bildanhang