Error (10500): VHDL syntax error at 3BM6Vorw.vhdl(25) near text "3";  expecting an identifier
Error (10500): VHDL syntax error at 3BM6Vorw.vhdl(32) near text "3";  expecting an identifier

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY 3BM6Vor IS
  PORT (clk: IN std_ulogic;
        srst_n: IN std_ulogic;
        a: IN std_ulogic_vector(0 DOWNTO 0);
        q: OUT std_ulogic_vector(2 DOWNTO 0));
END 3BM6Vor;

ARCHITECTURE behave OF 3BM6Vor IS

TYPE state_type IS (1, 2, 3, 4, 5, 6);
SIGNAL next_state, current_state : state_type;

-- comments for syf which comes with alliance : http://www-asim.lip6.fr/alliance
-- interpreted as comments by other tools
  --pragma CURRENT_STATE current_state
  --pragma NEXT_STATE next_state
  --pragma CLOCK clk

BEGIN
  state_register: PROCESS (clk)
  BEGIN
    IF ( clk = '1' AND NOT clk'STABLE ) THEN
      current_state <= next_state;
    END IF;
  END PROCESS;

  next_state_and_output_logic: PROCESS (current_state, a)
  BEGIN
    IF srst_n='0' THEN 
        next_state <= 1;
    ELSE
    CASE current_state IS
      WHEN 1 => q <= "001";
        IF a="0" THEN
          next_state <= 2;
        ELSIF a="1" THEN
          next_state <= 1;
        END IF;
      WHEN 2 => q <= "010";
        IF a="0" THEN
          next_state <= 3;
        ELSIF a="1" THEN
          next_state <= 2;
        END IF;
      WHEN 3 => q <= "011";
        IF a="0" THEN
          next_state <= 4;
        ELSIF a="1" THEN
          next_state <= 3;
        END IF;
      WHEN 4 => q <= "100";
        IF a="0" THEN
          next_state <= 5;
        ELSIF a="1" THEN
          next_state <= 4;
        END IF;
      WHEN 5 => q <= "101";
        IF a="0" THEN
          next_state <= 6;
        ELSIF a="1" THEN
          next_state <= 5;
        END IF;
      WHEN 6 => q <= "110";
        IF a="0" THEN
          next_state <= 1;
        ELSIF a="1" THEN
          next_state <= 6;
        END IF;
      WHEN OTHERS => null;
    END CASE;
    END IF;
  END PROCESS;

END behave;