Figure 64. Parallel Programming Timing, Including some General Timing Requirements Characteristics X LW L X H X L XTAL1 D V X H tX LD X Data & Contol (DATA, XA0, XA1/BS2 PAGEL/BS1) tB V W L W LW H W LB X WR W LR L RDY/BSY tW LR H 118 ATtiny26(L) 1477K–AVR–08/10 ATtiny26(L) (1) Figure 65. Parallel Programming
10uF/50V 10uF/25V AMSRB-7815-NZ 10uF/50V 10uF/25V Ripple and Noise Reduction +V input 1 3 +V output L AMSRB-78Z C1 C2 22uF 2 Ground Ground Recommended value of inductor L is between 10uH to 47uH www.aimtec.com Tel: +1 514 620 2722 Toll free: + 1 888 9 AIMTEC (924 6832) F 051e R12.C 2 of 3 North America
and Wake-up Sources in the Different Sleep Modes Active Clock Domains Oscillators Wake-up Sources d l k a e o E d n M O o t S C e a h O y I d u P L O D i r 0 C M P a C e t r lC lF lI l a o N i P E e D t a n Sleep Mode c c c c M S I P S E R A O W I Idle X X X X X X X X ADC Noise X X X(1) X X X Reduction
swapped, the current in the live wire is less than that in the neutral. Figure 9. Partial Earth Fault. L N METER ITOT I1 R L1 I2 R L1 LOAD The firmware constantly monitors current flow in both wires and signals an earth fault if the magnitude difference between the two exceeds a given a threshold. The threshold
detected brge fault ;within 130ms then exit sbic PIND,INPUT ;Wait for start bit rjmp start1 clr timerL ;Measure length of start bit start2: cpi timerL,17 ;If startbit longer than 1.1ms, brge fault ;exit sbis PIND,INPUT rjmp start2 ;Positive edge of 1st start bit mov temp,timerL ;timer is 1/2 bit time clr timerL mov ref1,temp lsr ref1 mov ref2,ref1 add ref1,temp ;ref1 = 3/4 bit time lsl temp add ref2,temp ;ref2 = 5/4 bit time start3: cp timerL,ref1 ;If high period St2 > 3/4 bit time brge fault ;exit sbic PIND
OC1B) PB6 16 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 33 PG0(WR) 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 B G G E C N L L D D D D D D D D ) / P S V G T T P P P P P P P P C 2 1 R X X 0 1 ) 2 3 1 1 1 2 ) C S C N N N N ( C ( T( / O O L / 1 1 ( 2 T T C D D D C ( ( X T ( ( ( Overview The ATmega128 is a low-power CMOS 8-bit
Sources in the Different Sleep Modes Active Clock Domains Oscillators Wake-up Sources e b c n g g H l E d a M / o p U A C C c a h / O y r h u C F I A i u 0 C M P a C e t e Sleep Mode l l l l a o N ni P E e D t a n c c c c M S I P S E R A O W I Idle X X X X X X X X ADC Noise Reduction X X X(1) X X X Power-down
SECTOR 0a = 8 Pages SECTOR 0a 2,048-/2,112-bytes BLOCK 1 PAGE 1 BLOCK 2 K 0 C SECTOR 0b = 248 Pages R L 63,488-/65,472-bytes T B C PAGE 6 S PAGE 7 BLOCK 30 PAGE 8 SECTOR 1 = 256 Pages BLOCK 31 65,536-/67,584-bytes BLOCK 32 PAGE 9 K BLOCK 33 C SECTOR 2 = 256 Pages R L 65,536-/67,584-bytes O B C PAGE 14
. 4768B–INDCO–10/05 Figure 1-1. Block Diagram with Typical Circuit, Period Group Control 0 to 100% L D 1 220 kΩ R2 R 18 kΩ/ Load 1 2 W 1000 W (250 V~) (sync -VS C R 2 4 2 8 5 C1 100 kΩ 100 µF/ 2.2 µF/ 1 Ramp 7 16 V VM= 230 V~ 10 V Synchronization Supply generator GND R5 MT2 12 kΩ 3 + 6 100 Ω MT1 max
AVR444 Figure 1. Waveforms P1 P2 P3 P4 P5 P6 ZC ZC U V [ F ZC ZC M E V - c a B ZC ZC W ] U V [ e g t l v V n i a v t W c A The floating phase, where the zero crossing must be detected, changes for every commutation step. One ADC channel for each phase winding is needed to detect zero crossings. 2.2 Startup
Small Outline (JEDEC SOIC) 19 3347I–SEEPR–1/05 8A2 – TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A D 2.90 3.00 3.10 2, 5 b E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 e A2 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 D e 0.65 BSC Side View L 0.45 0.60 0.75 L1 1.00 REF Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not
M NOTE: Bottom pad should be soldered to ground. 0 1 1 A B S O A 2 O 1 S A 4 / I NI C C C O IS C T L T / 2 N 0 / A3 / / / / M/ / IN / I 2 O C C 0 2 K 1 S 2 T 2 P 0T P I 3 ( 1 C N L N / C I T ( I ( C N 2 2 IC 0 C T / C I C ( C N 2 ( T ( I T ( P ( ( C N I P I ( ( C P ( C ( ( ( 2 8271BS–AVR–04/10 ATmega48A
Robert L. schrieb im Beitrag #1839178: > jetzt nicht wundern, eine fußbodenheizung ist SOO träge, das man min. 3 > stunden Verzögerung hat, ... Das kommt entscheidend aufs System an, da er keinen Neubau
>KL2722 was kostet das ? 50€ für 2 ausgäng?? da wäre ja sogar EIB/KNX billiger.. >Wie mache ich dann die Einzelraumregelung per SPS? Da brauche ich doch >dann auch für jeden Raum einen Temperatursensor
Bereich uC. Momentan arbeite ich an einem ISM Funkmodem. Als Transceiver Baustein habe ich mir den ML2722 ausgesucht. http://www.rfmd.com/CS/Documents/ML2722_ML2722SPACEDatasheet.pdf Microlinear wurde von rfmd aufgekauft und den im Devellopment Kit verwendeten uC gibts nicht mehr (habe ihn zumindest
sind und worauf ich achten muss. Die Daten sollen via rs485 bzw rj45 Schnittstelle als TTP_CHxL TTP_CHxH zum/vom Modem gesendet werden. (kommen von einem TTP Bus) Der Transceiver hat CMOS Eingangslogik für serielle Daten und Konfiguration 16Bit. Es soll die mögliche max. Datenrate angestrebt
starts is shown. Figure 3-4. Speed ramp limited by desired speed value ω decel_val speed el cc de a e i l _ l x e t a c step m a • max_s_lim is the number of steps needed to accelerate to the desired speed. speed 2 max_s_lim = n = 2α ⋅accel⋅100 • accel_lim is the number of steps before deceleration starts
100% Kurzschlußfestigkeit erforderlich ist kann man natürlich auch Leistungsoperationsverstärker wie L2722/L272 (Reichelt) oder TCA0372 o.ä. verwenden. Gruß Anja
Evtl. ein L6201 (H-Brückentreiber), da sind in einem Gehäuse schon 2 Treiber (mit genügend Dampf). Zu klären wäre hier, aber High- oder Lowside getaktet werden MUSS wegen Boot-Kondensator. Der L6234 hat 3 Halbbrücken
modulation Forward driving S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 U V W H1 H2 H3 hal 3 2 6 4 5 1 3 2 6 4 5 1 l Reverse driving S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 U V W H1 H2 H3 hal 3 1 5 4 6 2 3 1 5 4 6 2 l 3.4 Timing All available timer/counter units in the ATmega48 are used for PWM generation. For that reason
XMEGA A1 32. Packaging information 32.1 100A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 Notes: 1. This package
pins of the AVR can be determined empirically or it can be estimated by Equation 5-1. Equation 5-1. C L1 ⋅C L2 C L = +C S C L + C L 2 Where C L1 and C L2 referrers to the external capacitors seen in Figure 5-1 and C is S the combined capacitive load of the XTAL pins of the AVR and stray capacitances of
L Takes the radio transceiver into RX_AACK_ON state and enables CLKM PLL_ON TX start L Æ H Starts frame transmission TX_ARET_ON TX start L Æ H Starts TX_ARET transaction In states PLL_ON and TX_ARET_ON
and Wake-up Sources in the Different Sleep Modes Active Clock Domains Oscillators Wake-up Sources d l k a e o E d n M O o t S C e a h O y I d u P L O D i r 0 C M P a C e t r lC lF lI l a o N i P E e D t a n Sleep Mode c c c c M S I P S E R A O W I Idle X X X X X X X X ADC Noise X X X(1) X X X Reduction
(TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data
C 4 m e R L L r m C C 4 - T p R D t t C V e 0 O S 2 E L 3 l n V n 3 / T W P 3 3 g t 2 2 o D G O f P T D1 R 1k : e r ul R R m F O F o 1 t a 1 t r 6 R e d r a ef R 0 0 0 n f < g n t n rn d 1 1 o s 2 i o u g t 2 R
determined empirically or it can be estimated by Equation 5-1. Equation 5-1. C ⋅C ' C ' = C +C C = L1 L2 , L1 L1 L1S L C +C ' ' L1 L2 C L2 = C L2 +C L2S Where C L1and C L2 refer to the external capacitors seen in Figure 5-1 and C L1S and C L2Sare stray capacitances at the XTAL pins of the AVR. Assuming symmetric layout, so that C L1 = C L2 = C and C L1S = C L2S = C ,Sthen the external capacitors can be determined by Equation 5-2 (C cSn be estimated to be 5-10pF): Equation 5-2. C = 2⋅C −C L S 8 AVR042 2521F-AVR-04/08 AVR042 5.3
USBS0 UCSZ1 UCSZ01 UCSZ0 UCSZ00 UCPOL UCPOL0 UBRRH UBRR[11:8] UBRR0H UBRR0[11:8] UBRRL UBRR[7:0] UBRR0L UBRR0[7:0] 4 Memory The EEPROM write times are different, and can be seen Table 4-1 Table 4-1. Wait times when programming EEPROM Device Typical programming time ATmega169 8.5 ms ATmega169P 3.3 ms 5
determined empirically or it can be estimated by Equation 5-1. Equation 5-1. C ⋅C ' C ' = C +C C = L1 L2 , L1 L1 L1S L C +C ' ' L1 L2 C L2 = C L2 +C L2S Where C L1and C L2 refer to the external capacitors seen in Figure 5-1 and C L1S and C L2Sare stray capacitances at the XTAL pins of the AVR. Assuming symmetric layout, so that C L1 = C L2 = C and C L1S = C L2S = C ,Sthen the external capacitors can be determined by Equation 5-2 (C cSn be estimated to be 5-10pF): Equation 5-2. C = 2⋅C −C L S 8 AVR042 2521F-AVR-04/08 AVR042 5.3
, result.word2 4.47.3 Operation TRAP 21 4.47.4 Syntax I. f2l 4.47.5 Operands none 4.47.6 Format f2l ( 0x8c ) 4.47.7 Note The f2l instruction performs a narrowing primitive conversion. It may lose information about the overall magnitude of value, and may also lose
identifies the device. The three bytes reside in a separate address space, and for the ATtiny15L they are: 1. $000 : $1E (indicates manufactured by Atmel). 2. $001 : $90 (indicates 1 Kb Flash memory). 3. $002 : $06 (indicates ATtiny15L device when $001 is $90). 54 ATtiny15L 1187G–AVR–06/07 ATtiny15L
aufgebauten Schaltung im Anhang steuert ein Mega8 einen 12V Getriebemotor, sogar recht direkt über L2722 verbunden um den Strom zu messen, und da stört sich nichts, selbst ohne Entstörglied am Motor würde sich nichts stören.
B A v 6 R 1 4 ] . f [ o 1 P 1 2 0 t 5 e K S G T T 4 3 S V 5 5 P P R 0 1 K O 2 1 F 0 R 4 I I N 1 R L L I e D D A m Z v N x 2 x 2 Z L e o E R T E A b , R 3 4 E 4 5 M , u a G D D R J J 2 M t s 2 1 1 5 C e n 2 T N m > e 7 P S O c o W T T , D < R S 6 I T T e e t x 7 i i A a T 8 T S D 3 C Q B T T V 1 K V
determined empirically or it can be estimated by Equation 5-1. Equation 5-1. C ⋅C ' C ' = C +C C = L1 L2 , L1 L1 L1S L C +C ' ' L1 L2 C L2 = C L2 +C L2S Where C L1and C L2 refer to the external capacitors seen in Figure 5-1 and C L1S and C L2Sare stray capacitances at the XTAL pins of the AVR. Assuming symmetric layout, so that C L1 = C L2 = C and C L1S = C L2S = C ,Sthen the external capacitors can be determined by Equation 5-2 (C cSn be estimated to be 5-10pF): Equation 5-2. C = 2⋅C −C L S 8 AVR042 2521F-AVR-04/08 AVR042 5.3
convection Humidity 95 % Case material Non-conductive black plastic UL94-VO Weight 1.8 g Dimensions (L x W x H) 0.46 x 0.24 x 0.38 inches11.68 x 6.00 x 9.65 mm MTBF >1 191 000 hrs (MIL-HDBK -217F, Ground Benign, t=+25 C) NOTE: All specifications are measured at an ambient temperature of 25°C, humidity
AT89C51 Flash Programming Modes Mode RST PSEN ALE/PROG EA/V PP P2.6 P2.7 P3.6 P3.7 Write Code Data H L H/12V L H H H Read Code Data H L H H L L H H Write Lock Bit - 1 H L H/12V H H H H Bit - 2 H L H/12V H H L L Bit - 3 H L H/12V H L H L Chip Erase H L H/12V H L L L (1) Read Signature Byte H L H H L L L L Note: 1. Chip Erase requires a 10 ms PROG pulse. Figure 3. Programming the Flash Figure 4. Verifying the Flash +5V +5V AT89C51 AT89C51 ADDR. A0 - A7 P1 VCC ADDR. A0 - A7 P1 VCC OOOOH/OFFFH PGM OOOOH
