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xc2200_um_v2.1_2008_08_vol2per.pdf
Input Signal Limits System Clock = 10 MHz Input GPT1 Input System Clock = 40 MHz Frequ. Divider Phase Max. Input Min. Level Factor BPS1 Duration Max. Input Min. Level Frequency Hold Time Frequency Hold Time 1.25 MHz 400 ns GPT/8 01 B 4 × GPT 5.0 MHz 100 ns 625.0 kHz 800 ns GPT/16 00 B 8 × GPT 2.5 MHz 200
in „Schlechte Datenblätter von Infineon (CAN)“ · Mikrocontroller und Digitale Elektronik ·
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SAM-V71Q-SAM-V71N-SAM-V71J_Datasheet.pdf
12-layer AHB Bus Matrix M f 150 MHz MAX 42 SAM V71 [DATASHEET] Atmel-44003E-ATARM-SAM V71-Datasheet_12-Oct-16 10. Product Mapping Figure 10-1. SAM V71 Product Mapping 0x00000000 Address memory space 0x00000000 Code ITCM or Boot Memory Code
in „Atmel SAMV71 CAN FD“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Noname.map.txt
Middlewares/MotorControl/speed_torq_ctrl.o 0x00000000080054ce STC_GetMecSpeedRefUnitDefault .text.STC_GetMaxAppPositiveMecSpeedUnit 0x00000000080054d4 0x4 Middlewares/MotorControl/speed_torq_ctrl.o 0x00000000080054d4 STC_GetMaxAppPositiveMecSpeedUnit .text.STC_GetMinAppNegativeMecSpeedUnit 0x00000000080054d8
in „Problem mit STM32F103 und RAM-Größe“ · Mikrocontroller und Digitale Elektronik ·
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TC1797_UM_v1.1.pdf
Instruction Result Repeat Latency Rate Latency Rate Integer Pipeline Arithmetic Instructions ABS 1 1 MAX.H 1 1 ABS.B 1 1 MAX.HU 1 1 ABS.H 1 1 MAX.U 1 1 ABSDIF 1 1 MIN 1 1 ABSDIF.B 1 1 MIN.B 1 1 ABSDIF.H 1 1 MIN.BU 1 1 ABSDIFS 1 1 MIN.H 1 1 ABSDIFS.H 1 1 MIN.HU 1 1 ABSS 1 1 MIN.U 1 1 ABSS.H 1 1 RSUB 1 1
in „TC1797 - keine Datenblätter?“ · Mikrocontroller und Digitale Elektronik ·
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stm32l431_reference_manual.pdf
. . . . . . . . . 207 6.4.18 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 208 6.4.19 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 210 6.4.20 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 212 6.4.21 AHB1 peripheral clocks enable
in „ADC differential mode“ · Mikrocontroller und Digitale Elektronik ·
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stm32l431_reference_manual.pdf
. . . . . . . . . 207 6.4.18 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 208 6.4.19 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 210 6.4.20 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 212 6.4.21 AHB1 peripheral clocks enable
in „Offset Data alignment“ · Mikrocontroller und Digitale Elektronik ·
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stm32l431_reference_manual.pdf
. . . . . . . . . 207 6.4.18 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 208 6.4.19 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 210 6.4.20 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 212 6.4.21 AHB1 peripheral clocks enable
in „DMA one shot mode“ · Mikrocontroller und Digitale Elektronik ·
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PIC16F18344.pdf
and only the modulated output CWGxD is affected. T = --------------- DBx 4:0> + 1 DEAD – BAND_MAX FCWG_CLOCK The CWGxDBF register determines the duration of the dead-band interval on the falling edge of the input source signal. This duration is from zero to 64 periods of the CWG clock. T JITTER= T DEAD – BAND_MAX – TDEAD – BAND_MIN Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no dead T = - ------------- JITTER FCWG_CLOCK band is present. If the input source
in „EEPROM Verständnisproblem beim PIC 16F18344“ · Mikrocontroller und Digitale Elektronik ·
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Datei
rawsource.asm
ZL sts zx_ram+0x35,ZH libmio_isf1: lds XL,zx_ram+0x0c ;DFILE addr lds XH,zx_ram+0x0d andi XH,0x3f ;max 16K subi XH,0xfe ;start at 0x0200 libmio_isf2: adiw XL,1 ;skip first HALT sts libmio_rampos_l,XL sts libmio_rampos_h,XH lds ZL,libmio_keycode ldi ZH,HIGH(libmio_zktable) lsl ZL rol ZH lpm XL,Z+ lpm
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slau144i.pdf
Rotate Right Through Carry RRC.B and RRC.W ............................................................208..... 4-41. Swap Bytes in Memory ......................................................................................215......... 4-42. Swap Bytes in a Register ....................................
in „Anfängerprogramm TimerA MSP430“ · Mikrocontroller und Digitale Elektronik ·
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UM10398_-_LPC11xx_UserManual.pdf
register 0 Table 34 STARTERP0 R/W 0x204 Start logic signal enable register 0 Table 35 STARTRSRP0CLR W 0x208 Start logic reset register 0 n/a Table 36 STARTSRP0 R 0x20C Start logic status register 0 n/a Table 37 - - 0x210 - 0x22C Reserved - - UM10398 All information provided in this document is subject © NXP
in „Cortex-M UART im Polling-Betrieb“ · Mikrocontroller und Digitale Elektronik ·
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MC9S08DZ60_Data_Sheet.pdf
MSCAN Bus Timing Register 1 (CANBTR1) ...............................................................208 12.3.5 MSCAN Receiver Interrupt Enable Register (CANRIER) .............................................211 12.3.6 MSCAN Transmitter Flag Register (CANTFLG) ..........................................
in „Bei AD-wandlung Bitsverlust“ · Mikrocontroller und Digitale Elektronik ·
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xe166_um_v2.1_2008_08_vol2per.pdf
Input Signal Limits System Clock = 10 MHz Input GPT1 Input System Clock = 40 MHz Frequ. Divider Phase Max. Input Min. Level Factor BPS1 Duration Max. Input Min. Level Frequency Hold Time Frequency Hold Time 1.25 MHz 400 ns GPT/8 01 B 4 × GPT 5.0 MHz 100 ns 625.0 kHz 800 ns GPT/16 00 B 8 × GPT 2.5 MHz 200
in „Kernel State Configuration Register KSCCFG xe164 xe166 xe164f xe16x“ · Mikrocontroller und Digitale Elektronik ·
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4620.pdf
TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST= 1024 clock cycles. TPLL≈ 2 ms max. First three stages of the PWRT timer. 2004 Microchip Technology Inc. Preliminary DS39626B-page 47 PIC18F2525/2620/4525/4620 4.6 Reset State of Registers Table 4-4 describes the Reset states for all
in „SPI master/slave - schreib/lese befehle ?“ · Mikrocontroller und Digitale Elektronik ·
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Mikrocontroller-PIC18F2420.pdf
8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39631E-page 124 © 2008 Microchip Technology Inc. PIC18F2420/2520/4420/4520 11.3 Prescaler 11.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0
in „Spannungseinbruch beim Sampeln des Signals“ · Mikrocontroller und Digitale Elektronik ·
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Datei
report_all.txt
/DCM1_INST/Using_Virtex.DCM_INST:CLK0 | 2541 | microblaze_own_IP_III_i/mdm_0/mdm_0/drck_i | BUFG | 208 | microblaze_own_IP_III_i/mdm_0/bscan_update1 | BUFG | 42 | fpga_0_clk_1_sys_clk_pin | clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST:CLK2X+clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST:CLK0
in „Place and Route partially locked IO bus“ · FPGA, VHDL & Co. ·
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PIC18f6622.pdf
17-3: (T4CON). FOSC logFPWM- 5. Configure the CCPx module for PWM operation. PWM Resolution (max) = ---------bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency
in „PIC 18F6622 Zeit um EEPROM zu schreiben“ · Mikrocontroller und Digitale Elektronik ·
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PIC_18F8722_Data_Sheet.pdf
17-3: (T4CON). ⎛FOSC ⎞ log⎝FPWM-⎠ 5. Configure the CCPx module for PWM operation. PWM Resolution (max) = ---------bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency
in „PIC 18F6527 mit 32MHz Takten“ · Mikrocontroller und Digitale Elektronik ·
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version_1p3_assembler.lst
96: ;***************************************************************************** 97: ; 98: ; The max. value for XTAL is now 78627473 Hz, for use BASIC-52 with 99: ; Dallas 80C320 high speed / low power microcontroller (33 MHz). ASEM-51 V1.3 Copyright (c) 2002 by W.W. Heinz PAGE 3 Line I Addr Code Source
in „Basic für 80C31“ · Mikrocontroller und Digitale Elektronik ·
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PIC18F46J11_39932D.pdf
hardware integrity checking and • Tunable Internal Oscillator (31 kHz to 8 MHz, ±0.15% Typical, ±1% Max). safety interlocks prevent unintentional • 4x PLL Option configuration changes • Hardware Real-Time Clock and Calendar (RTCC): • Secondary Oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor
in „PIC18F46J11 und RTC. Quarz nötig? Anfängerfrage Übersicht verloren ;-(“ · Mikrocontroller und Digitale Elektronik ·
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H83003H.PDF
Features (cont) Feature Description Operating modes Four MCU operating modes Address Address Initial Bus Max. Bus Mode Space Pins Width Width Mode 1 1 Mbyte A to A 8 bits 16 bits 0 19 Mode 2 1 Mbyte A 0to A19 16 bits 16 bits Mode 3 16 Mbyte A 0to A23 8 bits 16 bits Mode 4 16 Mbyte A 0to A23 16 bits 16 bits
in „H8/300 Frage (genauer H8/3003)“ · Mikrocontroller und Digitale Elektronik ·
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R8C22-23_Group_Hardware_Manual.pdf
clock Period of CPU clock Following total (flash memory time is the time operates) × 12 cycles + 30µs (max.) × 6 cycles × 20 cycles from wait mode until an interrupt 1 Period of system clock (flash memory × 12 cycles Same as above Same as above routine is stops) executed. T1 T2 T3 Flash memory activation
in „Fragen zu Renesas µC (R5F2122CKFP)“ · Mikrocontroller und Digitale Elektronik ·
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rej09b0101_16c29hm_2_.pdf
2007 page 36 of 458 REJ09B0101-0112 M16C/29 Group 5. Resets VCC ROC td(P-R) More than td(ROC) RESET Max. 2 ms CPU clock: 28 cycles CPU clock FFFFC16 Content of reset vector Address FFFFE16 Figure 5.2 Reset Sequence ____________ Table 5.1 Pin Status When RESET Pin Level is “L” Pin name Status P0 to P3,
in „Zeitproblem bei Softwarepwm“ · Mikrocontroller und Digitale Elektronik ·
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avrdude_out.txt
Size #Pages MinW MaxW ReadBack ----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- --------- hfuse 0 0 0 0 no 1 0 0 9000 9000 0x00 0x00 Block Poll Page Polled Memory Type Mode Delay Size Indx Paged Size
in „avrdude braucht lange zum Beenden (Linux)“ · Compiler & IDEs ·
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64F3048F16-Hitachi.pdf
input-only pins Operating modes Seven MCU operating modes Mode Address Space Address Pins Initial Bus Width Max. Bus Width Mode 1 1 Mbyte A19to A0 8 bits 16 bits Mode 2 1 Mbyte A to A 16 bits 16 bits 19 0 Mode 3 16 Mbytes A23to A0 8 bits 16 bits Mode 4 16 Mbytes A to A 16 bits 16 bits 23 0 Mode 5 1 Mbyte A19to
in „CPU Melkanlage auslesbar? 64F3059F16“ · Mikrocontroller und Digitale Elektronik ·
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MC9S12XF512.pdf
Table 7-7. FDIV vs XTAL Frequency XTAL Frequency (MHz) XTAL Frequency (MHz) FDIV[6:0] FDIV[6:0] MIN 1 MAX 2 MIN1 MAX 2 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90
in „Wie oft kann ein µC programmiert werden?“ · Mikrocontroller und Digitale Elektronik ·
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MC9S12XF512.pdf
Table 7-7. FDIV vs XTAL Frequency XTAL Frequency (MHz) XTAL Frequency (MHz) FDIV[6:0] FDIV[6:0] MIN 1 MAX 2 MIN1 MAX 2 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90
in „Probleme beim Ansteuern eines EEPROM über SPI“ · Mikrocontroller und Digitale Elektronik ·
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8020rev26.pdf
Start LO as is PointA1h -AFh Convert to hex 1st / Last / Start LO Point B0h Convert to hex Lead Out Max Point B1h - BFh Convert to hex Skip Values Point C0h Convert to hex ORP /App Code Point C1h - FFh No conversion Reserved working draft ATAPI Page 173 Revision 2.5 ATAPI Packet Commands for CD-ROM devices
in „CD-ROM Laufwerk“ · Mikrocontroller und Digitale Elektronik ·
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PDF
INF-8020.pdf
Start LO as is PointA1h -AFh Convert to hex 1st / Last / Start LO Point B0h Convert to hex Lead Out Max Point B1h - BFh Convert to hex Skip Values Point C0h Convert to hex ORP /App Code Point C1h - FFh No conversion Reserved working draft ATAPI Page 173 Revision 2.5 ATAPI Packet Commands for CD-ROM devices
in „ATAPI Packet Commands“ · Mikrocontroller und Digitale Elektronik ·
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slau144j.pdf
affected Z: Set C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. 208 CPUX SLAU144J–December 2004–Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com Instruction Set Description 4.6.2.46 SUB SUB[.W] Subtract
in „MSP430 Gleitkommazahl in Flash speichern“ · Mikrocontroller und Digitale Elektronik ·
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family_guide.pdf
affected Z: Set C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. 208 CPUX SLAU144J–December 2004–Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com Instruction Set Description 4.6.2.46 SUB SUB[.W] Subtract
in „MSP430 Output nur auf zwei von vier Pinnen möglich?“ · Mikrocontroller und Digitale Elektronik ·
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PIC32MX3XX_Data_Sheet.pdf
bits Note 1: This register contains the value of the most recent active DMA channel. DS61143E-page 208 Preliminary © 2008 Microchip Technology Inc. PIC32MX3XX/4XX REGISTER 10-3: DMAADDR: DMA ADDRESS REGISTER (1) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR<31:24> bit 31 bit 24 R-0 R-0 R-0 R-0 R-0 R-0 R-0
in „PIC32 und Assembler“ · Mikrocontroller und Digitale Elektronik ·