-
Datei
spi_master.vhd
- dw10_cs <= '0'; -- when x"10" => -- dw00_cs <= '0'; -- dw04_cs <= '0'; -- dw08_cs <= '0'; -- dw0c_cs <= '0'; -- dw10_cs <= '1'; -- when others => -- dw00_cs <= '0'; -- dw04_cs <= '0'; -- dw08_cs <= '0'; -- dw0c_cs <= '0';
in „unklares Signalverhalten eines SPI-Moduls“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
ADCModule.vhd
downClk6Counter_var : INTEGER range 0 to 3 := 0; VARIABLE barVec : STD_LOGIC_VECTOR(barSteps-1 downto 0) := (others => '0'); VARIABLE count : INTEGER := 0; VARIABLE my_line : line; begin if (rising_edge(clk)) then if(amplifyPhase = '0') then case counter is when 0 => ad_conv_en_var := '0'; spi_clk_en_var := '0';
-
Datei
random_cellular.vhd
(left, middle, right : bit) return bit is variable tmp : bit; begin case left & middle & right is when "110" => tmp := '1'; when "101" => tmp := '1'; when "011" => tmp := '1'; when "010" => tmp := '1'; when "001" => tmp := '1'; when others => tmp := '0'; end case; return tmp; end CA; signal pattern_old : bit_vector(0 to 15):= (others => '0'); signal pattern_new : bit_vector(0 to 15):= (others => '0'); signal sync1, set_seed : bit := '0'; signal counter : integer range 0 to 16 := 0; begin --synchronise set_seed by two flip_flops
-
Datei
sr_adc4.vhdl
serial and internal clock process (cs, i_clock) begin if (cs = '0') then aConv <= '0'; odChA <= (others=>'0'); odChB <= (others=>'0'); elsif rising_edge(i_clock) then sCounter <= sCounter + 1; sr <= sr(sr'left-1 downto 0) & aData; case sCounter is when 0 => if (doADC = '1') then aConv <= '1'; end if;
in „Der vhdl-Schnipsel-Anfängerfragen Thread“ · FPGA, VHDL & Co. ·
-
Datei
PWM.vhd
(s_ctr, reset_n) begin if reset_n ='1' then --asynchroner Reset v_o <= '0'; s_led <= (others => '1'); s_state <= IDLE; else case s_state is when IDLE => -- STOP if pause_i = '1' then s_state <= PAUSE; elsif play_i = '1' then s_state <= PLAY; elsif stop_i = '1' or eof_i = '1' then s_state <= IDLE; else s_state <= IDLE; end if; v_o <= '0'; s_ctr <= (others => '0'); s_led <= s_led or "10000000"; when PLAY => if pause_i = '1' then s_state <= PAUSE; elsif play_i = '1' then s_state <= PLAY; elsif stop_i = '1' or eof_i = '1' then s_state <= IDLE; else s_state
in „HILFE, ich finde nicht raus wo der Fehler liegt!“ · FPGA, VHDL & Co. ·
-
PDF
Against-Tithing-John-Owen-80.pdf
and there is no mention therein of the genealogies of the patriarchs who were of that lineage from when e Christ did come ; but when it makes mention of any others, though beginning of his days, or the end of his life. Whatever, therefore they be never so eminent, it reckoned not up their genealogy Thu
-
Datei
mini_merge_data.vhd
state_output_logic : process(i_reset,i_data_valid_s,w_state_reg,w_index_reg,i_data_s) begin case w_state_reg is when idle => o_state <= (1 => '1', others => '0'); -- validation o_busy <= '0'; if (i_reset = '1') then w_state_next <= idle; w_index_next <= (others => '0'); o_data_long <= (others => '0'); o_next_data
in „Counter in FSM zählt nach synthese falsch“ · FPGA, VHDL & Co. ·
-
Datei
SN74HC595_1.vhd
initcounter +1; else if div < 511 then div <= div +1; else if data_1 /= reg then reg <= data_1; div <= (others => '0'); end if; end if; end if; end process; SN74HC595_1_SER <= reg(to_integer(div(7 downto 5))) when div < 256 else '0'; SN74HC595_1_SRCLK <= div(4) when div < 256 else '0'; SN74HC595_1_RCLK <= '1' when div > 256 and div < 256+20 else '0'; end Behavioral;
-
Datei
lcd.vhd
- process (pclk, Blank) begin if (Blank = '0') then scount <= (others => '0'); elsif (pclk' event and pclk = '0') then scount <= scount + 1; end if; end process; -------------------------------- -- PixelSel -------------------------------- process (R,G,B, InSel(2 downto 0)) begin case InSel(2 downto 0) is when "000" => sdata <= R; when "001" => sdata <= G; when "010" => sdata <= B; when "011" => sdata <= R AND G AND B; when "100" => sdata <= R OR G OR B; when others => sdata <= '0'; end case; end process;
-
Datei
Rs232Tx.vhd
; end if; end if; end if; when DataBufferBusy => if (BitStrobe = '1') then case (R.Region) is when StopBitAndIdle => NextR.Tx <= cTxLineStopBitAndIdleVal; NextR.DataInputState <= CanAcceptNewData; when StartBit => NextR.BitIdx <=
in „Xilinx ISE Mehrfach-Instanzierung Bug(?)“ · FPGA, VHDL & Co. ·
-
PDF
1.0_OLED_REX012864CWAP3N00000_white.603913.pdf
Series MPU: This is the read/write control signal input terminal. When R/W = “H”: Read. When R/W = “L”: Write. Page 7 , Total 27 Pages This is a MPU interface input pad. When connected to an 8080 series MPU, it is active LOW. This pad is connected to the RD signal of the 8080 series MPU, and the data bus is in an output status when this signal is “L”. 17 RDB When connected to a 6800 series MPU , this is active HIGH. This is used as an enable clock input of the 6800 series MPU. When RD = “H”: Enable. When RD = “L”: Disable. 18
in „SH1106 Init-Sequenz“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
DTA124E-D.pdf
Marking. STYLES ON PAGE 2 DOCUMENT NUMBER: 98ASB42226B Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOT−23 (TO−236) PAGE 1 OF 2 onsemi and are trademarks of
in „Bauteil identifzieren“ · Analoge Elektronik und Schaltungstechnik ·
-
Datei
i2c.vhd
or previous no-acknowledge ack_error <= '1'; --set error output if no-acknowledge END IF; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; --set sda output WITH state SELECT sda_ena_n <= data_clk WHEN start, --generate start condition NOT data_clk WHEN stop, --generate stop condition sda_int WHEN OTHERS; --set to internal sda signal --set scl and sda outputs scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z'; sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z'; END logic;
in „De0-Nano Accelerometer: keine Antwort“ · FPGA, VHDL & Co. ·
-
Datei
Loopback.vhd
= '1' THEN -- Synchronous reset. state <= s_Idle; s_rx_ack <= '0'; s_tx_ack <= '0'; s_output <= (OTHERS => '0'); s_buffer <= (OTHERS => '0'); ELSE CASE state IS WHEN s_Idle => IF s_rx_rdy = '1' THEN s_buffer <= s_rx_data; -- s_rx_ack <= '1'; state <= s_Read; ELSE s_rx_ack <= '0'; s_tx_ack <= '0'; --s_output <= (others => '0'); --s_buffer <= (others => '0'); END IF; WHEN s_Read => s_rx_ack <= '0'; -- Debug! (Lothar M.) s_output <= x"55"; state <= s_Write; -- End Debug! -- Vereinfachte Dekodierung in Kommando/Datenbyte
in „UART Kommandos funktionieren nicht“ · FPGA, VHDL & Co. ·
-
Datei
SR_24Bit.vhd
<= Counter +1; else if Start = '1' then TX_Reg <= Data; Counter <= (others => '0'); end if; end if; end process; Ready <= '1' when Start = '0' and Address > 25 else '0'; TX <= TX_Reg(to_integer(Address)) when Address < 24 else '0'; ShiftCLK <= Counter(3) when Address < 24 else '0'; LatchCLK <= '1' when Address = 25 else '0'; end Behavioral;
-
Datei
log2.vhd
! logzero <= '1'; dout <= (others => '0'); drdy <= '1'; else state := STATE_SHIFT; sr := din; end if; end if; when STATE_SHIFT => if sr(15) = '1' then ram_addr <= sr(14 downto 7); state := STATE_LUT; else sr := sr(14 downto 0) & '0
-
Datei
ALU.vhd
" => Y <= YMulti; when "0100" => Y <= NOT Ob; when "0101" => Y <= Oa AND Ob; when "0110" => Y <= Oa OR Ob; when "0111" => Y <= Oa XOR Ob; when "1000" => Y <= Oa NAND Ob; when "1001" => Y <= Oa NOR Ob; when "1010" => Y <= Oa XNOR Ob; when "1011" => Y <= Ob + 1; when "1100" => Y <= Ob - 1; when "1101" => NULL; when others => NULL; end case; end process; end Behavioral;
in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. ·
-
Datei
fsm.vhd
(taster(8) = '1') then next_state <= S9; end if; when S9 => if (timer = 0) then next_state <= S0; end if; end case; end process; process(next_state) begin case next_state is when S0 => led <= (others => '1'); when S1 => led <= "11000000"; when S2 => led <= "11100000"; when S3 => led <= "11110000"; when S4 => led <= "11111000"; when S5 => led <= "11111100"; when S6 => led <= "11111111"; when S7 => led <= "00000011"; when S8 => led <= "00000111"; when S9 => led <= (others
in „Automaten(FSM) und die verschiedenen Prozess Modelle“ · FPGA, VHDL & Co. ·
-
Datei
Enigma.vhd
found : boolean; begin read_write : process (clock, reset, init) begin if reset = '1' then rotor <= (others => (others => '0')); elsif init = '1' then position <= rotor'left; elsif rising_edge(clock) then if write_enable = '0' and read_enable = '1' and lookup = '1' then found <= false; -- Search all entries
-
Datei
framewrapper.vhd
<= '1'; end if; when SEND_BOF => sig_disconnected <= '0'; READ_TX_FIFO <= '1'; sig_send_bof <= '0'; sig_write_uart <= '1'; -- var_state := SEND_DATA; -- end if; when SEND_DATA => if sig_no_more_data = '1' then -- READ_TX_FIFO
in „State Machine: undefinierter Zustand.“ · FPGA, VHDL & Co. ·
-
Datei
framewrapper.vhd
<= '1'; end if; when SEND_BOF => sig_disconnected <= '0'; --READ_TX_FIFO <= '1'; sig_send_bof <= '0'; -- sig_write_uart <= '1'; var_state := SEND_DATA; when SEND_DATA => if sig_no_more_data = '1' then READ_TX_FIFO <= '0
in „State Machine: undefinierter Zustand.“ · FPGA, VHDL & Co. ·
-
Datei
Rs232Rx.vhd
iDataRead : in std_ulogic; -- data was read from internal fifo oErrFlag : out std_ulogic); -- set when receiving error occurs, disabled when receiving continues end entity Rs232Rx; architecture RTL of Rs232Rx is type aRs232RxFifo is array (0 to gRxFifoSize-1) of std_ulogic_vector(gBitWidth-1 downto 0
in „Xilinx ISE Mehrfach-Instanzierung Bug(?)“ · FPGA, VHDL & Co. ·
-
Datei
uart_rx.vhd
) THEN IF rst = '1' THEN -- Synchronous reset. s_clk_count <= 0; s_bit_index <= 0; s_rx_data <= (OTHERS => '0'); s_rx_rdy <= '0'; state <= S_Idle; ELSE CASE state IS WHEN S_Idle => IF (s_shiftreg(1) <= '0') THEN -- Start bit detected. state <= S_Rx_Start_Bit; s_rx_rdy <= '0'; ELSE state <= S_Idle; END
in „UART Kommandos funktionieren nicht“ · FPGA, VHDL & Co. ·
-
Datei
taschenrechner.vhd
1'; --release code, nächste taste ignorieren when X"F0" => kybignore <= '1'; when others => end case; else --E0 ist zur unterscheidung Numblock gut. if ( kybreg /= X"E0" ) then kybignore <= '0'; end if; end if; kybstate <= waitidle; end if; when waitidle
in „VHDL Rechner“ · FPGA, VHDL & Co. ·
-
Datei
RS232_Mux.vhd
-- stop2 when others => if(BaudTick='1') then state <= "0000"; end if; end case; end process; process (state,TxD_dataD) begin case state(2 downto 0) is when "000" => muxbit <= TxD_dataD(0); -- bit 0 when "001" =>
-
Datei
Anzeige.vhd
; end if; end if; counter<=counter+"0000000000001"; if(counter > "1000000000000") then counter<=(others=>'0'); end if; end if; end process; Anzeigen: process(code) begin case code is when "0000" => LED <="1000000"; --0 when "0001" => LED <="1111001"; --1 when "0010" => LED <="0100100"; --2 when "0011
-
Datei
top_sub_melodyPlayer.vhd
not "10000000" , "000" when others ; -- melody2 with sequencerStep select note2 <= "000" when not "00000001" , "010" when not "00000010" , "101" when not "00000100" , "011" when not "00001000" , "101" when not "00010000" , "010" when not "00100000" , --"010" when not "01000000" , --"011" when not "10000000" , "000" when others ; end architecture;
-
Datei
I2S_Top.vhd
STD_LOGIC := '0'; signal TransmitData : STD_LOGIC_VECTOR(0 to ((DATA_WIDTH_PER_CHANNEL * 2) - 1)) := (others => '0'); -- Signal for Audio ROM signal ROM_Data : STD_LOGIC_VECTOR(0 to (DATA_WIDTH_PER_CHANNEL - 1)) := (others => '0'); signal ROM_Address : STD_LOGIC_VECTOR(6 downto 0) := (others => '0'); begin
-
Datei
toplevel.vhdl
false; if linectr >= 310 then linectr <= 0; else linectr <= linectr + 1; end if; case linectr is when 309 => vsync <= true; when 2 => vsync <= false; when others => null; end case; else pixelctr <= pixelctr + 1; newline <= '0'; case pixelctr is -- start of sync when 18 => hsync <= true; -- end of sync
in „Active-HDL: wie bekomme ich die Waveform angezeigt“ · FPGA, VHDL & Co. ·
-
Datei
I2S_tx.vhd
" else '1'; -- stretching txd signals for QSM mode l_txd <= l_txd_i or l_txd_reg when mclk_sel = '0' else l_txd_i; r_txd <= r_txd_i or r_txd_reg when mclk_sel = '0' else r_txd_i; mclk_div <= to_unsigned(4, mclk_div'length) when sr_sel_reg(3) = '1' else to_unsigned(3, mclk_div'length) when sr_sel_reg(2) = '1' else to_unsigned(2, mclk_div'length) when sr_sel_reg(1) = '1' else to_unsigned(1, mclk_div'length) when sr_sel_reg(0) = '1' else to_unsigned(1, mclk_div'length); -- MCLK/LRCLK =
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
-
Datei
FSM.txt
prüfen else zustand <= Z14; end if; when Z13 => zustand <= Z14;--Fehler when Z14 => zustand <= Z9; --Fertig when others => zustand <= Z1; end case ; end if; end process FSM; -- Ausgangsmatrix der FSM***************************************
-
Datei
arcCosFP.vhd
RANGE 0 TO 7:= 0; BEGIN IF rising_edge(clk) THEN IF nrst = '0' THEN state <= 0; cntrclk := 0; --(OTHERS => '0'); ELSE CASE state IS WHEN 0 => IF ceacos = '1' THEN ce1 <= '1';-- start für 1-x, x`2, ComP0.5 state <= 1; ELSE state <= 0; END IF; WHEN 1 => --- Ausführen 1-x,X`2,CompX ce1 <= '0'; ce2 <= '1
-
Datei
moore.vhd
next_state; end if; end if; end process; output_decode : process(state, yout_int) begin case(state) is when Idle => yout_int <= '0'; when A1 => when B1 => when C1 => when A11 => yout_int <= '0'; when B11 => yout_int <= '1'; when C11 => yout_int <= not yout_int; when others => yout_int <= '0'; end case; end
in „Probleme bei Vivado Tutorial mit State Machine“ · FPGA, VHDL & Co. ·
-
Datei
vga.vhd
else ball_x_s <= ball_x_s - vx_s; end if; end case; case state_y is when down => if ( ball_y_s > 600-20-vy_s ) then ball_y_s <= 600 - 20; state_y <= up; else ball_y_s <= ball_y_s + vy_s; end if; when up => if ( ball_y_s < vy_s ) then ball_y_s <= 0; state_y <= down; else
-
Datei
NiosII_ADXL345_spi_read.vhd
std_logic_vector(7 downto 0); -- export switch_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export key_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export gpio_external_connection_export : inout std_logic_vector(31 downto 0) := (others =>
-
PDF
vhdl.pdf
statement a 00 good case: process (a, b, c, d, sel) b 01 begin −− process bad if c 10 case sel is d 11 when ”00” => o <= a; when ”01” => o <= b; sel when ”10” => o <= c; when others => o <= d; Use case statement for end case; multiplexers end process good case; Best synthesis results Hardware Design with
-
Datei
gitarre.vhd
<= "1011" ; when others => dsp_puffer <= freq_puffer(15 downto 12) ; enable <= "0111" ; end case ; case dsp_puffer is when "0000" => seg <= "0000001"; when "0001" => seg <= "1001111"; when "0010" => seg <= "0010010"; when "0011" => seg <= "0000110"; when "0100" => seg <= "1001100"; when "0101" => seg <= "0100100"; when "0110" => seg <= "0100000"; when "0111" => seg <= "0001111"; when "1000" => seg <= "0000000"; when
in „Frequenzzähler+bad synchronous description.“ · FPGA, VHDL & Co. ·
-
Datei
gitarre_neu.vhd
<= "1011" ; when others => dsp_puffer <= freq_puffer(15 downto 12) ; enable <= "0111" ; end case ; case dsp_puffer is when "0000" => seg <= "0000001"; when "0001" => seg <= "1001111"; when "0010" => seg <= "0010010"; when "0011" => seg <= "0000110"; when "0100" => seg <= "1001100"; when "0101" => seg <= "0100100"; when "0110" => seg <= "0100000"; when "0111" => seg <= "0001111"; when "1000" => seg <= "0000000"; when
in „Frequenzzähler+bad synchronous description.“ · FPGA, VHDL & Co. ·
-
Datei
gitarre_neu.vhd
<= "1011" ; when others => dsp_puffer <= freq_puffer(15 downto 12) ; enable <= "0111" ; end case ; case dsp_puffer is when "0000" => seg <= "0000001"; when "0001" => seg <= "1001111"; when "0010" => seg <= "0010010"; when "0011" => seg <= "0000110"; when "0100" => seg <= "1001100"; when "0101" => seg <= "0100100"; when "0110" => seg <= "0100000"; when "0111" => seg <= "0001111"; when "1000" => seg <= "0000000"; when
in „Frequenzzähler+bad synchronous description.“ · FPGA, VHDL & Co. ·
-
Datei
atanFP.vhd
rising_edge(clk) THEN IF nrst = '0' THEN stateatan <= 0; cntrclk := 0; cecomp <= '0'; sign := "00"; --(OTHERS => '0'); ELSE CASE stateatan IS WHEN 0 => IF ceatan = '1' THEN IF (Yinp = X"00000000") AND (Xinp = X"00000000") THEN atanFP <= X"00000000"; stateatan <= 0;-- ungültige wert ELSE stateatan <= 1; END
-
Datei
HuffmanLu_encode.vhd
((DC_ADD_Code),7); index_a <= 13; when 8 => out_reg_a(95 downto 89) <= "1111110"; out_reg_a(88 downto 81) <= conv_std_logic_vector((DC_ADD_Code),8); index_a <= 15; when 9 => out_reg_a(95 downto 89) <= "1111111"; index_a <= 7; when others
-
Datei
FSM_2.vhd
std_logic_vector(6 downto 0); begin -- MUX mux: process (dig0, dig1, dig2, dig3, cnt) begin case cnt is when "00" => mux <= dig0; when "01" => mux <= dig1; when "10" => mux <= dig2; when "11" => mux <= dig3; when others => mux <= 0; end case; end process mux; -- FSM -- -- when start is '1', a sequence of 4
-
Datei
uart_transmit.vhd
uart_transmit; architecture Behavioral of uart_transmit is signal send_slow : unsigned (5 downto 0) := (others=>'0'); signal send_counter : unsigned (3 downto 0) := "1011"; -- "1011" -> idle signal ser_out_vector : std_logic_vector (8 downto 0) := (others=>'1'); signal enabled : std_logic := '0'; signal direction
in „Logicanalyzer für Pollin CPLD (HW+SW)“ · Projekte & Code ·
-
Datei
ADCModule.vhd
StateControl process. SIGNAL dataBuffer1, dataBuffer2 : STD_LOGIC_VECTOR(regBits-1 downto 0) := (others => '0'); --SIGNAL temp : INTEGER := 0; SIGNAL downClk6 : STD_LOGIC; SIGNAL AMP_SPI_SCK_EN : STD_LOGIC; -- states description: -- I defined here a Zero state as the state where both SPI_SCK and ad_conv
-
Datei
control_ram_version1.vhd
NEXT_STATE_WR <= WR_ADR_POST; elsif UPDATE = '0' then NEXT_STATE_WR <= STS_ADR_RD; end if; -- WR_ADR_POST when WR_ADR_POST => if s_wr_rdy = '0' and UPDATE = '0' then NEXT_STATE_WR <= WR_ADR_POST; end if; when others => null; end case; end process; ADR_COUNTER_WR: process begin wait until clk'event and clk =
in „[VHDL] Daten von ADC in BRAM speichern“ · FPGA, VHDL & Co. ·
-
Datei
EthernetTX.vhd
frameLength; when others => end case; when stSendFrameLowNybble => state <= stSendFrameHighNybble; txd <= txBuffer1(3 downto 0); crcByte <= '1'; if counter >= x"0006" then ethTXStrobe <= '1'; end if; when stSendFrameHighNybble
in „100MBit Ethernet mit Spartan 3E Starter Kit“ · FPGA, VHDL & Co. ·
-
Datei
EthernetTX.vhd
frameLength; when others => end case; when stSendFrameLowNybble => state <= stSendFrameHighNybble; txd <= txBuffer1(3 downto 0); crcByte <= '1'; if counter >= x"0006" then ethTXStrobe <= '1'; end if; when stSendFrameHighNybble
in „100MBit Ethernet mit Spartan 3E Starter Kit“ · FPGA, VHDL & Co. ·
-
Datei
i2c_controller.vhd
when X"8" => data2 <= X"02"; -- SAMPLE_CTRL when X"9" => data2 <= X"01"; -- SET_ACTIVE when others => state := D_IDLE; send <= '0'; end case; reg := reg + 1; end if; when D_SEND => if done = '1' then send
-
PDF
MERITEC-SMT-SOP-Sockets1.pdf
.615 P1 P2 63 250* 980020-56- 980020-56- 56 15.85 .624 13.50 .531 17.63 .694 P1 P2 56 250* *Note:when ordering tape andreel packaging,the part number should be followed by the letter“K.” * Note: when ordering tape and reel packaging, the part number should be followed by the letter "K" CONFIDENTIAL
in „NAND Chip TSOP48 mit einer Fassung verbauen“ · Platinen ·
-
Datei
lcd.vhd
; write_lcd <= '1'; when data3 => lcd_data <= x"73"; state_lcd <= data4; write_lcd <= '1'; when data4 => lcd_data <= x"74"; state_lcd <= lcdok; write_lcd <= '1'; when lcdok => null; when others => state_lcd <= lcdreset; end
in „Ansteuerung LCD Display(Spartan3E)“ · FPGA, VHDL & Co. ·