B S July 2002 S 8 4 BSS84 P-Channel Enhancement Mode Field Effect Transistor Features General Description These P-Channel enhancement mode field effect • −0.13A, −50V. R DS(ON) 10Ω @ V GS= −5 V transistors are produced using
Zelle 2 Zelle 3 Zelle 4 Wassermelder und Bedienung R7 GND 1k F R13 n 10k Q1 X2-1 +3V3 X8-4 +3V3 7 0 BSS84 C 1 X8-5 WASSER X8-3 FLÄCHE1 R14 NTC-VERSORGUNG NTC-VERSORGUNG MESSGND 10k GND X8-2 +3V3 R8 T 1 S 0 0 e 1k RSENSE- RSENSE+ O T 0 1 5 1 4 X8-1 FLÄCHE2 d e C2 C1 C3 B 3 R R w n 100nF 100nF 100nF GND
1 S Q B 3 J4 UEXT Bus power supply 1 2 4 k 5 k 3V3 GND R 2 R 2 UEXT_TX 3 TXD RXD 4 UEXT_RX Q7 5 6 BSS84 UEXT_SCL 7 SCL SDA 8 UEXT_SDA GND F3 D9 CAN_V+ UEXT_MISO MISO MOSI UEXT_MOSI D C DCDC_OUT 2 3 UEXT_SCK 9 SCK SSEL 10 UEXT_SSEL S S 200mA 1N4148 T T 9 k D8 E E R 5 MM3Z12VT1G 1 C U U R30 D10 C CAN_GND 56k 1N4148 3 R48 T3 GND V_BUS_EN 1 MMBT3904 10k 5V signal output 2 +5V Q5 BSS84 GND 2 3 5V_OUT 3 0 R 1 1 R38 MPPT Charger 20A 2.2k 3 R47 T4 5V_OUT_EN 1 MMBT3904 100k 2 Website: http://libre.solar D Sheet: /Communication Interfaces/ D File: interfaces.sch GND Author: Martin Jäger
Display1 +9V +5V +5V +9V +5V LCD_2x8A IC1 1 +9V T4 LP2950 R2 K1 BSS84 V W D D 2 2 3 3 IN OUT 1 k 0 + V R R E D D D D D D D D L L E E 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 1 2 GND 2 1 1 1 K 2 0 2 C 1 + S 5 4 N 9 6 1 C1 R N 0 1 1 C1 1 3V/10mA: 0OHM K µ 2 D 1 1 R 5
THS6214 OFF: 75 Vc V V 1N4148 G R11 R17 R21 D5 , 3 , 3 BIAS2 TR1 1k 30 6 R 4 R Q10 X1 T4-1T-X65 R19 X3 BSS84 1N4148 6 T2 k 4 IN2 6 1 D R 4 2,2k C 1 56k , R 2 N 5 0 n - 2 BU-SMA 4 3 G R 1 R20 BU-SMA e 8 C16 2 1 2 3 R39 7 3 C10 BN61-202 6/4T l T 4 C L 4 R 4 Gehäuse: AKG 55 20 80 ME GND 2,2k GND C K R 100n 3
L BTS555 can be switched on with jumper E 9 4 on P1 if everything fails H 1 R A S 3 N I Q5 I V 1 BSS84 S A K 1 +5V _ P1 0 C 0 5 2 0 R C 1 1 1 R JP3 3 M 2 0 _ N C5 C49 C50TSENSE T 3 N E K 7 3 B C Sense enable network for BQ34. D 6 R Q3 0 9 0 R if not needed can be shorted with JP3 100nFI 1 100nF3,3nF
L BTS555 can be switched on with jumper E 9 4 on P1 if everything fails H 1 R A S 3 N I Q5 I V 1 BSS84 S A K 1 _ P1 0 C 0 5 2 0 R C 1 1 1 R JP3 3 M 2 0 _ N C5 C49 C50TSENSE T 3 N E K 7 3 B C Sense enable network for BQ34. D 6 R Q3 0 9 if not needed can be shorted with JP3 100nFI 1 100nF3,3nF ALARM 1
ISL28133 BZX70-4V R9 Q3 D1 100Ω Source follower is stable. +12V1 + A PNP can be used for VIN - - BSS84 better headroom, but it has = SHUNT /R9 some beta-related error. TO µC/ADC LOAD R8 R7 10kΩ 10kΩ ISL28133: Ultra low 8µV Bias requirement is 25µA for amp plus zener bias. offset, rail-to-rail input/
1n e t C e N 1 47k r N 4 4 LM4040 r . 47u k k 10k 10k 10k e . 0 S e 2 4,7 uH 330k 1 8 3 R 1M e P BSS84 R7 e k 2 6 2 ( B 5 ( T 9 T e e 10k l l 2 1 ) M ) U B Wannenstecke0 B k s B ü e c t u c n a k a 8 g e n e z d - g - e o d o O m e m b n r n e r ü r s 3 c 3 e k R e e 2 ( t T e Batteriehalter i 3 ) m
discharge when EPD power off VST 1 Q3 VGL 100K/5% 100K/5% 1 R3 R2 D1 VCOM SS2040FL R5 100K/5% 2 3 BSS84W Q4 Connect to Timing Controller GPIO BORDER_CONTROL 1 2 VCC BORDER Control: Square Pulse when power on Note : 1. V and V must be discharged promptly after power off DD CC 2. 2.7" Pin.1 location (1,1
discharge when EPD power off VST 1 Q3 VGL 100K/5% 100K/5% 1 R3 R2 D1 VCOM SS2040FL R5 100K/5% 2 3 BSS84W Q4 Connect to Timing Controller GPIO BORDER_CONTROL 1 2 VCC BORDER Control: Square Pulse when power on Note : 1. V and V must be discharged promptly after power off DD CC 2. 2.7" Pin.1 location (1,1
discharge when EPD power off VST 1 Q3 VGL 100K/5% 100K/5% 1 R3 R2 D1 VCOM SS2040FL R5 100K/5% 2 3 BSS84W Q4 Connect to Timing Controller GPIO BORDER_CONTROL 1 2 VCC BORDER Control: Square Pulse when power on Note : 1. V and V must be discharged promptly after power off DD CC 2. 2.7" Pin.1 location (1,1
discharge when EPD power off VST 1 Q3 VGL 100K/5% 100K/5% 1 R3 R2 D1 VCOM SS2040FL R5 100K/5% 2 3 BSS84W Q4 Connect to Timing Controller GPIO BORDER_CONTROL 1 2 VCC BORDER Control: Square Pulse when power on Note : 1. V and V must be discharged promptly after power off DD CC 2. 2.7" Pin.1 location (1,1
BORDER discharge when EPD power off VST 1 Q3 VGL 100K/5% 100K/5% 1 R3 R2 D1 VCOM SS2040FL R5 100K/5% 2 BSS84W 3 Q4 Connect to Timing Controller GPIO BORDER_CONTROL 1 2 VCC BORDER Control: Square Pulse when power on Note: (1) V DD and V CC must be discharged promptly after power off. Rev.: 01 Page: 19 of 29
varicap SM BB914 Sie B SOT23 dual varicap for FM radio SR BSS131 Sie M SOT23 n-ch mosfet 240V 0.1A SP BSS84 Sie M SOT23 p-ch mosfet 50V 0.13A SS BSS138 Sie M SOT23 n-ch mosfet 50V 0.22A ST BSS139 Sie M SOT23 n-ch dep mosfet 250V 0.04A Codes beginning with 'T' Code Device Manufacturer Base Package Leaded
circuit using the SAFE output to blow a fuse is shown in Figure 5. FUSE BAT+ V CC Cell 4 1 MΩ 0.1 µF BSS84 100 kΩ 2N7002 SAFE 1 MΩ Figure 5. Example SAFE Circuit Implementation 19 www.ti.com bq2085 SLUS541 – OCTOBER 2002 Low-Power Modes The bq2085 enters sleep mode when the charge and discharge current
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
