1 | -- Bresenham.vhd
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_arith.all;
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4 | use ieee.std_logic_unsigned.all;
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5 |
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6 | ENTITY Bresenham IS
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7 | generic
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8 | (
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9 | SHIFT_WIDTH : natural := 1
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10 | );
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11 | PORT
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12 | (
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13 | clk : in std_logic;
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14 | reset_n : in std_logic;
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15 | fval_in : in std_logic;
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16 | lval_in : in std_logic;
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17 | pval_in : in std_logic;
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18 | ref_in : in std_logic_vector(15 downto 0);
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19 |
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20 | ref_out : out std_logic_vector(15 downto 0);
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21 | fval_out : out std_logic;
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22 | lval_out : out std_logic;
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23 | pval_out : out std_logic;
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24 | rdref : out std_logic
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25 |
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26 | );
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27 | END Bresenham;
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28 |
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29 | ARCHITECTURE behavior OF Bresenham IS
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30 |
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31 | signal r_fval : std_logic_vector(SHIFT_WIDTH-1 downto 0);
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32 | signal r_lval : std_logic_vector(SHIFT_WIDTH-1 downto 0);
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33 | signal r_pval : std_logic_vector(SHIFT_WIDTH-1 downto 0);
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34 |
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35 | signal r_ref : std_logic_vector(11 downto 0);
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36 | signal r_ref_in : unsigned(15 downto 0):=(others => '0');
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37 | signal r2_ref_in : integer := 0;
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38 | signal r3_ref_in : integer := 0;
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39 | signal ref_result : std_logic_vector(15 downto 0):=(others => '0');
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40 |
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41 | signal state : std_logic:='0';
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42 |
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43 | BEGIN
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44 |
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45 | ref_out <= ref_result;
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46 | fval_out <= r_fval (SHIFT_WIDTH-1);
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47 | lval_out <= r_lval (SHIFT_WIDTH-1);
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48 | pval_out <= r_pval (SHIFT_WIDTH-1);
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49 | rdref <= state;
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50 |
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51 |
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52 | process(reset_n, clk)
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53 | variable x1 : unsigned(7 downto 0):=(others => '0');
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54 | variable y1 : unsigned(7 downto 0):=(others => '0');
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55 | variable ex : integer := 0;
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56 | variable ex1 : integer := 0;
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57 | variable x : integer := 0;
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58 | variable y : integer := 0;
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59 | begin
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60 |
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61 | if(reset_n = '0') then
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62 | r_fval <= conv_std_logic_vector('0', SHIFT_WIDTH);
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63 | r_lval <= conv_std_logic_vector('0', SHIFT_WIDTH);
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64 | r_pval <= conv_std_logic_vector('0', SHIFT_WIDTH);
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65 | r_ref <= (others => '0');
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66 | r2_ref_in <= 0;
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67 | r3_ref_in <= 0;
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68 | r_ref <= (others => '0');
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69 | r_offset <= (others => '0');
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70 | ref_result <= (others => '0');
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71 |
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72 | elsif(clk'event and clk = '1') then
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73 | r_fval <= r_fval (SHIFT_WIDTH-2 downto 0) & fval_in;
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74 | r_lval <= r_lval (SHIFT_WIDTH-2 downto 0) & lval_in;
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75 | r_pval <= r_pval (SHIFT_WIDTH-2 downto 0) & pval_in;
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76 | ref_result1 <= ref_result;
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77 |
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78 | if (fval_in = '1' and lval_in ='0') then
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79 | r_ref_in <= unsigned (ref_in);
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80 | r2_ref_in<= conv_integer (r_ref_in (7 downto 0));
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81 | r3_ref_in<= conv_integer (r_ref_in (15 downto 8));
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82 | ex := r2_ref_in/2;
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83 | state <= '0';
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84 | end if;
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85 | if (lval_in ='1') then
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86 | if (state = '0') then
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87 | if (x <= r2_ref_in) then
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88 | if (ex < 0) then
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89 | y := y + 1;
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90 | ex := ex + r2_ref_in - r3_ref_in;
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91 | x1 := conv_unsigned(x,8);
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92 | y1 := conv_unsigned(y,8);
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93 | ref_result ( 7 downto 0) <= std_logic_vector(x1);
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94 | ref_result (15 downto 8) <= std_logic_vector(y1);
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95 | x := x + 1;
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96 | if (x > r2_ref_in) then
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97 | state <= '1';
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98 | else
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99 | state <= '0';
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100 | end if;
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101 | else
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102 | ex := ex - r3_ref_in;
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103 | x1 := conv_unsigned(x,8);
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104 | y1 := conv_unsigned(y,8);
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105 | ref_result ( 7 downto 0) <= std_logic_vector(x1);
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106 | ref_result (15 downto 8) <= std_logic_vector(y1);
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107 | x := x + 1;
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108 | if (x > r2_ref_in) then
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109 | state <= '1';
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110 | else
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111 | state <= '0';
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112 | end if;
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113 | end if;
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114 | elsif(x > r2_ref_in) then
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115 | state <= '1';
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116 | else
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117 | ref_result ( 7 downto 0) <= x"00";
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118 | ref_result (15 downto 8) <= x"00";
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119 | end if;
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120 | end if;
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121 | if (state = '1') then
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122 | ref_result ( 7 downto 0) <= std_logic_vector(x1);
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123 | ref_result (15 downto 8) <= std_logic_vector(y1);
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124 | end if;
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125 | else
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126 | x := 0;
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127 | y := 0;
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128 | state <= '0';
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129 | end if;
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130 | end if;
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131 | end process;
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132 | END behavior;
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