Frage zur Testbench

signal ADC_1_CLK : std_logic := '0';

signal ADC_2_CLK : std_logic := '0';

:

   ADC_1_CLK <= not ADC_1_CLK after 1.25 ns;

   ADC_2_CLK <= ADC_1_CLK after 1 ns;

:

-- Beschreibung

-- Generiert einen verjitterten Clock für Testbenches

library ieee;

use ieee.std_logic_1164.all;

use ieee.math_real.all;

entity jittered_clk_tbmod is

generic

(

   random_initial   : positive -- Jede Zahl an dieser Stelle erzeugt eine andere Random-Folge für den Jitter

);

port

(

   clk_rate         : in  natural;   -- Taktrate in Hz

   clk_dutycycle    : in  real;      -- Typischer Weise 0.5

   clk_jitter       : in  real;      -- max. "clk_dutycycle / 2" oder "(1-clk_dutycycle) / 2"

   -- Ausgang

   clk_out          : out std_logic := '0'

);

end jittered_clk_tbmod;

architecture behavior of jittered_clk_tbmod is

   signal nom_clock     : std_logic;                        -- Nominaler Grundtakt

   signal random_seed1  : positive := random_initial;       -- Hilfssignale für Zufalssignalgenerierung

   signal random_seed2  : positive := random_initial+1;

   signal random_jitter : real     := 0.1;

begin

   nom_clock_proc: process

   begin

      nom_clock <= '0';

      wait for 1 ns;

      nom_clock <= '1' after (0.5 sec / clk_rate) - 1 ns;

      wait for (1.0 sec / clk_rate) - 1 ns;

   end process;

   master_clk_proc: process

      variable vseed1, vseed2 : positive;

      variable vjitter        : real;

   begin

      wait until rising_edge(nom_clock);

      vseed1     := random_seed1;

      vseed2     := random_seed2;

      vjitter    := random_jitter;

      uniform(vseed1, vseed2, vjitter);

      clk_out <= '0';

      clk_out <= '1' after (vjitter * clk_jitter + 0.25) * 1.0 sec / clk_rate;

      wait until falling_edge(nom_clock);

      uniform(vseed1, vseed2, vjitter);

      clk_out <= '0' after (vjitter * clk_jitter + clk_dutycycle - 0.25) * 1.0 sec / clk_rate;

      random_seed1  <= vseed1;

      random_seed2  <= vseed2;

      random_jitter <= vjitter;

   end process;

end behavior;