Array in Entity

[Stephan (Gast)]

Hallo zusammen,

ich möchte gerne in meiner Entity ein Generic als Array-Typ definieren:

filter_coef_g : array( 0 to 3, 0 to 3 ) of std_logic_vector;

Dieser Code besteht leider den Syntaxcheck nicht.

Gibt es eine Lösung ohne ein Package benutzen zu müssen?

Vielen Dank und Grüße
Stephan

[Duke Scarring (Gast)]

Stephan schrieb:
> Dieser Code besteht leider den Syntaxcheck nicht.
Kannst Du uns die komplette Datei, inklusive Fehlermeldung zur Verfügung 
stellen?

Duke

[Stephan (Gast)]

Hej,

hier hab ich die Entity.

entity generic_fir is
  Generic (
          taps_g           : positive := 3; -- number of filter taps
        poly_g           : positive := 2; -- number of polyphases
filter_coef_g : array( 0 to 3, 0 to 3 ) of std_logic_vector;       
        addr_width_g     : positive := 1; -- width of coefficient address
        din_width_g      : positive := 18; -- width of data in
        dout_width_g     : positive := 36; -- width of data out
        coef_width_g     : positive := 18; -- width of coefficients
        coef_str_width_g : positive := 20; -- field width of coefficients inside init string; coefficients assumed right-justified
        marker_width_g   : positive := 1; -- width of marker port
        channel_g        : positive := 1); -- number of input channels
  
    Port ( clk : in  STD_LOGIC;
           ce : in STD_LOGIC; -- unused
           din : in STD_LOGIC_VECTOR(din_width_g-1 downto 0);             -- data input
           en_in  : in  STD_LOGIC;                                      -- data enable                    
           marker_in : in STD_LOGIC_VECTOR(marker_width_g-1 downto 0);    -- marker in 
           calc_en_in : in STD_LOGIC;                                   -- filter enable
           addr_in : in STD_LOGIC_VECTOR(addr_width_g-1 downto 0);        -- address line for polyphase
           dout : out STD_LOGIC_VECTOR(dout_width_g-1 downto 0);          -- filter output
           calc_en_out : out STD_LOGIC;                                 -- filter output valid
           marker_out : out STD_LOGIC_VECTOR(marker_width_g-1 downto 0);  -- marker out; delayed marker in signal
           rst : in STD_LOGIC);                                         -- rst signal, not used because fitler is operated in streaming mode
end generic_fir;

Der Fehler ist folgender:
Line 36. parse error, unexpected ARRAY

und bezieht sich genau auf die beschriebene Codezeile!
Vielleicht ist eine solche Konstruktion auch nicht VHDL konform.

Vielen Dank

[Duke Scarring (Gast)]

Ich fürchte Du kommst da um ein package nicht drumherum. Ich würde es 
z.B. so machen:

package generic_fir_pack is

  type filter_coef_t is array(0 to 3, 0 to 3) of natural;

end package generic_fir_pack;


library ieee;
use ieee.std_logic_1164.all;

use work.generic_fir_pack.all;


entity generic_fir is
  generic (
    taps_g           : positive := 3;   -- number of filter taps
    poly_g           : positive := 2;   -- number of polyphases
    filter_coef_g    : filter_coef_t;
    addr_width_g     : positive := 1;   -- width of coefficient address
    din_width_g      : positive := 18;  -- width of data in
    dout_width_g     : positive := 36;  -- width of data out
    coef_width_g     : positive := 18;  -- width of coefficients
    coef_str_width_g : positive := 20;  -- field width of coefficients inside init string; coefficients assumed right-justified
    marker_width_g   : positive := 1;   -- width of marker port
    channel_g        : positive := 1    -- number of input channels
    );
  port (
    clk         : in  std_logic;
    ce          : in  std_logic;                                    -- unused
    din         : in  std_logic_vector(din_width_g-1 downto 0);     -- data input
    en_in       : in  std_logic;                                    -- data enable                    
    marker_in   : in  std_logic_vector(marker_width_g-1 downto 0);  -- marker in 
    calc_en_in  : in  std_logic;                                    -- filter enable
    addr_in     : in  std_logic_vector(addr_width_g-1 downto 0);    -- address line for polyphase
    dout        : out std_logic_vector(dout_width_g-1 downto 0);    -- filter output
    calc_en_out : out std_logic;                                    -- filter output valid
    marker_out  : out std_logic_vector(marker_width_g-1 downto 0);  -- marker out; delayed marker in signal
    rst         : in  std_logic                                     -- rst signal, not used because fitler is operated in streaming mode
    );
end generic_fir;

Duke

[Stephan (Gast)]

Ok, das hatte ich schon geahnt. Trotzdem vielen Dank.