1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.all;
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3 | use IEEE.STD_LOGIC_ARITH.all;
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4 | use ieee.numeric_std.all;
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5 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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6 |
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7 | --
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8 | -- onewirebit
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9 | -- onewirebit is the implementation of the lowest protocol
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10 | -- layer, the bit layer. This entity is able to send bit to
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11 | -- the bus and receive bity from the bus.
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12 | --
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13 |
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14 | entity onewirebit is
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15 | port(
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16 | CLK : in bit; -- system clock
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17 | dq : inout std_logic; -- route this to the physical pin connected to the onewire bus
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18 | reset : in bit; -- set this bit to '1' to send a reset condition, if a slave is present invalue will be set to '1', otherwise to '0'
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19 | writing : in bit; -- set this bit to '1' to start write process, one clock later clear this bit, after that for finished becoming '1'
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20 | outvalue : in bit; -- set this bit to the value to be written to the bus. Do not change this value while the entity is writing this value!
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21 | readbit : in bit; -- set this bit to '1' to read a bit from the bus
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22 | invalue : out bit; -- after finishing the readbit command, the readed value can be read here. Alternative it is used for the return value of reset.
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23 | finished : out bit -- after setting writing or readbit to '1' wait after one cycle for this bit to become '1' again
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24 | );
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25 | end onewirebit;
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26 |
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27 | architecture Behavioral of onewirebit is
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28 | type states is (state_idle, state_reset0, state_reset1, state_reset2, state_wb, state_rb0, state_rb1, state_finished);
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29 | signal state : states := state_idle;
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30 | signal timer : std_logic_vector (31 downto 0) := (others=>'0');
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31 | signal dq_outvalue : bit;
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32 | signal dq_invalue : bit;
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33 | begin
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34 | process(CLK)
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35 | begin
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36 | if CLK='1' and CLK'event then
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37 | timer <= timer + '1'; -- increment the timer each cycle
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38 | --invalue <= dq_invalue;
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39 | case state is
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40 | when state_idle =>
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41 | dq_outvalue <= '1';
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42 | finished <= '1';
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43 | if writing='1' then -- there is a new bit to be written to the bus
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44 | state <= state_wb;
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45 | timer <= (others => '0'); -- reset the timer for the next state
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46 | finished <= '0';
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47 | dq_outvalue <= '0'; -- pull down the line
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48 | elsif reset='1' then -- there is a reset to be executed
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49 | state <= state_reset0;
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50 | finished <= '0';
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51 | timer <= (others => '0'); -- reset the timer for the next state
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52 | dq_outvalue <= '0'; -- pull down the line
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53 | elsif readbit='1' then
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54 | state <= state_rb0;
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55 | end if;
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56 | when state_reset0 => -- wait fore reset time (500µs) to be over
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57 | if timer=std_logic_vector(to_unsigned(8000,timer'length)) then
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58 | state <= state_reset1;
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59 | timer <= (others => '0'); -- reset the timer for the next state
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60 | dq_outvalue <= '1'; -- release the line
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61 | end if;
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62 | when state_reset1 => -- the reset command has been sent, wait for slave responses after 70µs
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63 | if timer=std_logic_vector(to_unsigned(1120,timer'length)) then
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64 | invalue <= dq_invalue;
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65 | state <= state_reset2;
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66 | timer <= (others => '0'); -- reset the timer for the next state
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67 | end if;
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68 | when state_reset2 => -- the response has been recorded, wait for rising edge on the bus
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69 | if dq_invalue='1' then
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70 | state <= state_idle; -- go back to the idle state
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71 | end if;
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72 | when state_wb => -- the line is pulled low, pull it up after 10µs or 65µs µs, depending on outvalue
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73 | -- this two conditions could be made in one
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74 | -- outvalue should be buffered
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75 | if outvalue='1' and timer=std_logic_vector(to_unsigned(160,timer'length)) then -- when 10µs passed, release the line to write a logic one
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76 | dq_outvalue <= '1';
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77 | state <= state_finished;
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78 | timer <= (others => '0'); -- reset the timer for the next state
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79 | elsif outvalue='0' and timer=std_logic_vector(to_unsigned(1040,timer'length)) then -- when 65µs passed, release the line to write a logic zero
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80 | dq_outvalue <= '1';
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81 | timer <= (others => '0'); -- reset the timer for the next state
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82 | state <= state_finished;
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83 | end if;
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84 | when state_rb0 =>
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85 | when state_rb1 =>
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86 | when state_finished => -- wait 20µs for recovery and make shure the line is high (should be 2µs)
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87 | dq_outvalue <= '1';
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88 | if timer=std_logic_vector(to_unsigned(320,timer'length)) then
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89 | state <= state_idle;
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90 | finished <= '1';
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91 | end if;
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92 | end case;
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93 | end if;
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94 | end process;
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95 |
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96 | process(dq_outvalue, dq)
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97 | begin
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98 | if dq_outvalue = '1' then
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99 | dq <= 'Z';
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100 | else
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101 | dq <= '0';
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102 | end if;
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103 | --dq <= 'Z' when dq_outvalue='1' else '0';
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104 | --if dq='0' then
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105 | -- dq_invalue <= '0';
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106 | --else
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107 | -- dq_invalue <= '1';
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108 | --end if;
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109 | --dq_invalue <= '0' when dq='0' else '1';
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110 | end process;
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111 | dq_invalue <= to_bit(dq);
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112 | end Behavioral;
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