1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.STD_LOGIC_ARITH.ALL;
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4 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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5 |
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6 | library UNISIM;
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7 | use UNISIM.VComponents.all;
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8 |
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9 | entity x_blockram is
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10 | Port( DOA : out std_logic_vector(1 to 32); -- Port A
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11 | 32-bit Data Output
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12 | DOB : out std_logic_vector(1 to 32); -- Port B 32-bit
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13 | Data Output
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14 | DOPA : out std_logic_vector(1 to 4); -- Port A 4-bit
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15 | Parity Output
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16 | DOPB : out std_logic_vector(1 to 4); -- Port B 4-bit
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17 | Parity Output
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18 | ADDRA : in std_logic_vector(8 downto 0); -- Port A 9-bit
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19 | Address Input
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20 | ADDRB : in std_logic_vector(8 downto 0); -- Port B 9-bit
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21 | Address Input
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22 | CLKA : in std_logic;
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23 | CLKB : in std_logic; -- Port B Clock
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24 | DIA : in std_logic_vector(1 to 32); -- Port A 32-bit
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25 | Data Input
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26 | DIB : in std_logic_vector(1 to 32); -- Port B 32-bit
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27 | Data Input
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28 | DIPA : in std_logic_vector(1 to 4); -- Port A 4-bit
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29 | parity Input
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30 | DIPB : out std_logic_vector(1 to 4); -- Port-B 4-bit
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31 | parity Input
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32 | ENA : in std_logic; -- Port A RAM Enable Input
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33 | ENB : in std_logic; -- PortB RAM Enable Input
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34 | SSRA : in std_logic; -- Port A Synchronous
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35 | Set/Reset Input
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36 | SSRB : in std_logic; -- Port B Synchronous
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37 | Set/Reset Input
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38 | WEA : in std_logic; -- Port A Write Enable Input
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39 | WEB : in std_logic);
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40 | end x_blockram;
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41 |
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42 | architecture Behavioral of x_blockram is
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43 | -- RAMB16_S36_S36: Virtex-II/II-Pro, Spartan-3/3E 512 x 32 + 4
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44 | Parity bits Dual-Port RAM
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45 | -- Xilinx HDL Language Template version 7.1i
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46 |
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47 | RAMB16_S36_S36_inst : RAMB16_S36_S36
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48 | generic map (
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49 | INIT_A => X"000000000", -- Value of output RAM registers on
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50 | Port A at startup
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51 | INIT_B => X"000000000", -- Value of output RAM registers on
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52 | Port B at startup
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53 | SRVAL_A => X"000000000", -- Port A ouput value upon SSR
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54 | assertion
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55 | SRVAL_B => X"000000000", -- Port B ouput value upon SSR
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56 | assertion
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57 | WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
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58 | NO_CHANGE
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59 | WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
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60 | NO_CHANGE
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61 | SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING",
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62 | "GENERATE_X_ONLY", "ALL"
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63 | INIT_00 =>
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64 | X"0000000000000000000000000000000000000000000000000000000000000000",
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