Hallo zusammen
Ich wollte mich wieder ein wenig mehr mit VHDL auseinander setzten.
Dabei bin ich auf Generic gestossen, was doch recht interessant zu
schein scheint.
Doch als ich es ausprobieren wollte, scheiterte ich...
kann mir jemand weiterhelfen?
Die Datei parity_decoder.vhd
1 | entity parity_decoder is
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2 | Generic (bits : POSITIVE := 8);
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3 | Port ( input : in STD_LOGIC_VECTOR (bits-1 downto 0);
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4 | output : out STD_LOGIC);
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5 | end parity_decoder;
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6 |
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7 | architecture Behavioral of parity_decoder is
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8 | begin
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9 | process(input)
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10 | variable temp : STD_LOGIC;
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11 | begin
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12 | temp := '0';
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13 | for i in 0 to bits-1 loop
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14 | temp := temp xor input(i);
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15 | end loop;
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16 | output <= temp;
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17 | end process;
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18 | end Behavioral;
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Und dann noch test_parity_vhd
1 | entity test_parity is
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2 | Port ( test_in1 : in STD_LOGIC_VECTOR(7 downto 0);
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3 | test_in2 : in STD_LOGIC_VECTOR(3 downto 0);
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4 | test_out1 : out STD_LOGIC;
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5 | test_out2 : out STD_LOGIC);
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6 | end test_parity;
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7 |
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8 | architecture Behavioral of test_parity is
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9 | component parity_decoder
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10 | Generic (bits : POSITIVE);
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11 | Port ( input : in STD_LOGIC_VECTOR (bits-1 downto 0);
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12 | output : out STD_LOGIC);
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13 | end component;
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14 |
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15 | signal in1 : std_logic_vector(7 downto 0);
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16 | signal in2 : std_logic_vector(3 downto 0);
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17 | signal out1 : std_logic;
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18 | signal out2 : std_logic;
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19 | begin
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20 |
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21 | -- Komonenten instazieren
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22 | parity1 : parity_decoder
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23 | generic map (bits => 8)
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24 | port map(input => in1,
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25 | output => out1);
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26 |
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27 | parity2 : parity_decoder
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28 | generic map (bits => 4)
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29 | port map(input => in2,
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30 | output => out2);
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31 | -- Logik
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32 | process(test_in1, test_in2)
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33 | begin
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34 | in1 <= test_in1;
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35 | in2 <= test_in2;
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36 | test_out1 <= out1;
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37 | test_out2 <= out2;
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38 | end process;
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39 |
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40 | end Behavioral;
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in einer testbench werden die Signale test_out1 und test_out2 nie
gesetzt.
Besten Dank
Patrick