VHDL Code zu Register mit delay (Teillösung zu gelöschten Beitrag)

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity aufgabe1 is

    generic(

        TCO : integer := 8;

        N : integer := 32

    );

    port(

        clk : in  std_logic;

        ld : in  std_logic;

        clr : in std_logic;

        din : in std_logic_vector(N-1 downto 0);

        dout : out std_logic_vector(N-1 downto 0)

    );

end aufgabe1;

architecture behavior of aufgabe1 is

    type DIN_TYPE is array (0 to TCO-1) of std_logic_vector(N-1 downto 0);

    type register_file is record

        din : DIN_TYPE;

        counter : integer range 0 to TCO;

    end record;

    signal r : register_file; 

    signal rin : register_file := ((others => (others => '0')), 0);

begin

    comb: process(r, ld, clr, din)

        variable v : register_file;

    begin

        v := r;

        -- increase counter

        if (v.counter < TCO-1) then

            v.counter := v.counter + 1;

        else 

            v.counter := 0;

        end if;

        -- read in

        if (clr = '0') then

            if (ld = '1') then

                v.din(v.counter) := din;

            else 

                v.din(v.counter) := (others => '0');

            end if;

        else 

            dout <= (others => '0');

        end if;

        -- output

        if (v.counter >= TCO-1) then

            dout <= v.din(0);

        else 

            dout <= v.din(v.counter + 1);

        end if;

        rin <= v;

    end process;

    regs : process(clk)

    begin

        if rising_edge(clk) then

            r <= rin;

        end if;

    end process;

end architecture;