Hallo zusammen,
ich versuche gerade den Source von einer MIPS CPU von Verilog nach VHDL
umzusetzen. Meine Umsetzung scheint zu funktionieren, da die CPU
noch läuft :o)
Aber kann man die Umsetzung nach VHDL noch einfacher machen?
Hier nun der Verilog Source:
1 | module RegisterFile(
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2 | input clock,
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3 | input reset,
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4 | input [4:0] ReadReg1, ReadReg2, WriteReg,
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5 | input [31:0] WriteData,
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6 | input RegWrite,
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7 | output [31:0] ReadData1, ReadData2
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8 | );
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9 |
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10 | // Register file of 32 32-bit registers. Register 0 is hardwired to 0s
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11 | reg [31:0] registers [1:31];
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12 |
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13 | // Initialize all to zero
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14 | integer i;
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15 | initial begin
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16 | for (i=1; i<32; i=i+1) begin
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17 | registers[i] <= 0;
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18 | end
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19 | end
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20 |
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21 | // Sequential (clocked) write.
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22 | // 'WriteReg' is the register index to write. 'RegWrite' is the command.
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23 | always @(posedge clock) begin
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24 | if (reset) begin
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25 | for (i=1; i<32; i=i+1) begin
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26 | registers[i] <= 0;
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27 | end
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28 | end
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29 | else begin
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30 | if (WriteReg != 0)
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31 | registers[WriteReg] <= (RegWrite) ? WriteData : registers[WriteReg];
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32 | end
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33 | end
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34 |
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35 | // Combinatorial Read. Register 0 is all 0s.
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36 | assign ReadData1 = (ReadReg1 == 0) ? 32'h00000000 : registers[ReadReg1];
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37 | assign ReadData2 = (ReadReg2 == 0) ? 32'h00000000 : registers[ReadReg2];
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38 |
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39 | endmodule
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Und das ist meine Übersetzung:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 |
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5 | entity RegisterFile is
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6 | port (
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7 | clock : in std_logic := '0';
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8 | reset : in std_logic := '0';
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9 | ReadReg1 : in std_logic_vector(4 downto 0) := (others => '0');
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10 | ReadReg2 : in std_logic_vector(4 downto 0) := (others => '0');
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11 | WriteReg : in std_logic_vector(4 downto 0) := (others => '0');
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12 | WriteData : in std_logic_vector(31 downto 0) := (others => '0');
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13 | RegWrite : in std_logic := '0';
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14 | ReadData1 : out std_logic_vector(31 downto 0);
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15 | ReadData2 : out std_logic_vector(31 downto 0)
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16 | );
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17 | end entity RegisterFile;
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18 |
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19 | architecture syn of RegisterFile is
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20 |
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21 | type reg_t is array (0 to 31) of std_logic_vector(31 downto 0);
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22 | signal registers : reg_t := (others => (others => '0'));
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23 |
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24 | begin
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25 |
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26 | -- Sequential (clocked) write.
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27 | -- 'WriteReg' is the register index to write. 'RegWrite' is the command.
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28 | process (clock)
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29 | begin
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30 | if (rising_edge(clock)) then
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31 | if (reset = '1') then
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32 | for i in 1 to 31 loop
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33 | registers(i) <= (others =>'0');
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34 | end loop;
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35 | else
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36 | if (WriteReg /= "00000") then
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37 | if (RegWrite = '1') then
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38 | registers(to_integer(unsigned(WriteReg))) <= WriteData;
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39 | else
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40 | registers(to_integer(unsigned(WriteReg))) <= registers(to_integer(unsigned(WriteReg)));
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41 | end if;
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42 | end if;
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43 | end if;
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44 | end if;
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45 | end process;
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46 |
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47 | -- Combinatorial Read. Register 0 is all 0s.
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48 | ReadData1 <= x"00000000" when (ReadReg1 = "00000") else registers(to_integer(unsigned(ReadReg1)));
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49 | ReadData2 <= x"00000000" when (ReadReg2 = "00000") else registers(to_integer(unsigned(ReadReg2)));
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50 |
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51 | end architecture syn;
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Gibt es hier noch eine bessere Lösung als:
to_integer(unsigned(WriteReg))
Gruß,
Michael
