Hallo zusammen,
ich bin noch recht neu im Bereich der FPGAs / von VHDL und stehe vor
einem Problem (Warnung) die mich stark verwirrt. Ich habe folgenden Code
geschrieben:
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL;
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4 |
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5 | entity SimpleTest is
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6 | Port ( clk : in STD_LOGIC;
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7 | reset : in STD_LOGIC;
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8 | start : in STD_LOGIC;
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9 | --burst : in STD_LOGIC_VECTOR (11 downto 0);
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10 | frequenz : in STD_LOGIC_VECTOR (17 downto 0);
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11 | delay : in STD_LOGIC_VECTOR (15 downto 0);
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12 | out_signal : out STD_LOGIC);
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13 | end SimpleTest;
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14 |
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15 | architecture Behavioral of SimpleTest is
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16 | signal countDelay : unsigned(15 downto 0);
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17 | signal delayReady : std_logic;
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18 | signal countFreq : unsigned(17 downto 0);
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19 | signal temp_out : std_logic;
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20 | signal temp_ones : std_logic;
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21 |
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22 | begin
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23 | CTRD : process( clk, reset, delayReady, start )
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24 | begin
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25 | if reset = '0' then
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26 | countDelay <= (others => '0');
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27 | elsif clk='0' and clk'event and delayReady='0' and start='1' then
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28 | if countDelay < unsigned(delay) then
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29 | countDelay <= countDelay + 1;
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30 | else
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31 | countDelay <= (others => '0');
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32 | delayReady <= '1';
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33 | end if ;
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34 | end if ;
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35 | end process ; -- CTRD
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36 |
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37 | CTRF : process( clk, reset, delayReady, start )
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38 | begin
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39 | if reset = '0' then
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40 | countFreq <= (others => '0');
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41 | elsif clk='0' and clk'event and delayReady='1' and start='1' then
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42 | if delayReady='1' and temp_ones='0' then
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43 | temp_out <= '1';
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44 | temp_ones <= '1';
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45 | end if ;
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46 | if countFreq < unsigned(frequenz) then
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47 | countFreq <= countFreq + 1;
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48 | else
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49 | countFreq <= (others => '0');
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50 | temp_out <= not temp_out;
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51 | end if ;
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52 | end if ;
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53 | end process ; -- CTRF
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54 |
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55 | out_signal <= temp_out;
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56 |
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57 | end Behavioral;
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und bekomme die Warnungen:
1 | [Synth 8-3332] Sequential element (delayReady_reg) is unused and will be removed from module SimpleTest.
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2 | [Synth 8-3332] Sequential element (temp_ones_reg) is unused and will be removed from module SimpleTest.
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3 | [Synth 8-3332] Sequential element (\countDelay_reg[0] ) is unused and will be removed from module SimpleTest.
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4 | [Synth 8-3332] Sequential element (\countDelay_reg[1] ) is unused and will be removed from module SimpleTest.
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5 | [Synth 8-3332] Sequential element (\countDelay_reg[2] ) is unused and will be removed from module SimpleTest.
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6 | [Synth 8-3332] Sequential element (\countDelay_reg[3] ) is unused and will be removed from module SimpleTest.
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7 | [Synth 8-3332] Sequential element (\countDelay_reg[4] ) is unused and will be removed from module SimpleTest.
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8 | [Synth 8-3332] Sequential element (\countDelay_reg[5] ) is unused and will be removed from module SimpleTest.
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9 | [Synth 8-3332] Sequential element (\countDelay_reg[6] ) is unused and will be removed from module SimpleTest.
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10 | [Synth 8-3332] Sequential element (\countDelay_reg[7] ) is unused and will be removed from module SimpleTest.
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11 | [Synth 8-3332] Sequential element (\countDelay_reg[8] ) is unused and will be removed from module SimpleTest.
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12 | [Synth 8-3332] Sequential element (\countDelay_reg[9] ) is unused and will be removed from module SimpleTest.
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13 | [Synth 8-3332] Sequential element (\countDelay_reg[10] ) is unused and will be removed from module SimpleTest.
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14 | [Synth 8-3332] Sequential element (\countDelay_reg[11] ) is unused and will be removed from module SimpleTest.
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15 | [Synth 8-3332] Sequential element (\countDelay_reg[12] ) is unused and will be removed from module SimpleTest.
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16 | [Synth 8-3332] Sequential element (\countDelay_reg[13] ) is unused and will be removed from module SimpleTest.
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17 | [Synth 8-3332] Sequential element (\countDelay_reg[14] ) is unused and will be removed from module SimpleTest.
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18 | [Synth 8-3332] Sequential element (\countDelay_reg[15] ) is unused and will be removed from module SimpleTest.
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Aber ich benutze sie doch oder ?
folgender Test läuft ohne die Warnung:
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL;
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4 |
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5 | entity SimpleTest is
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6 | Port ( clk : in STD_LOGIC;
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7 | reset : in STD_LOGIC;
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8 | input_test : in STD_LOGIC;
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9 | max : in STD_LOGIC_VECTOR (15 downto 0);
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10 | output_test : out STD_LOGIC;
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11 | output_test2 : out STD_LOGIC);
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12 | end SimpleTest;
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13 |
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14 | architecture Behavioral of SimpleTest is
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15 | signal temp : std_logic;
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16 | signal count : unsigned(15 downto 0);
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17 |
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18 | begin
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19 | CTRD : process( clk, reset )
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20 | begin
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21 | if reset = '0' then
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22 | temp <= '0';
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23 | elsif clk='1' and clk'event then
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24 | if count <= unsigned(max) then
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25 | count <= count + 1;
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26 | else
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27 | count <= (others => '0');
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28 | temp <= not temp;
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29 | end if ;
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30 | end if ;
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31 | end process ; -- CTRD
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32 |
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33 | output_test <= temp;
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34 | output_test2 <= temp and input_test;
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35 |
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36 | end Behavioral;
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Kann mir jemand helfen?
Sry falls sich der Code etwas schrecklich liest aber ich stehe momentan
am Anfang des lernens ^^
