Ich bin VHDL-Anfänger und schaffe es einfach nicht, eine vierstellige
7-Segment-Anzeige anzusteuern (Beispiel reduziert):
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.STD_LOGIC_ARITH.ALL;
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4 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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5 |
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6 | entity Hello is
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7 | port ( SEG7 : out STD_LOGIC_VECTOR (1 to 8) := (others => '1');
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8 | ANODE : out STD_LOGIC_VECTOR (0 to 3) := (others => '0');
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9 | CLK : in STD_LOGIC);
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10 | end Hello;
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11 |
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12 | architecture V1 of Hello is
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13 | signal counter : STD_LOGIC_VECTOR (15 downto 0) := "1010010110010110";
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14 | signal seg7id : STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
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15 | begin
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16 | display: process(CLK)
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17 | variable digit : STD_LOGIC_VECTOR(3 downto 0);
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18 | begin
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19 | if rising_edge(CLK) then
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20 |
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21 | case seg7id is
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22 | when "00" => ANODE <= "1110";
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23 | digit := counter(3 downto 0);
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24 | seg7id <= "01";
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25 | when "01" => ANODE <= "1101";
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26 | digit := counter(7 downto 4);
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27 | seg7id <= "10";
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28 | when "10" => ANODE <= "1011";
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29 | digit := counter(11 downto 8);
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30 | seg7id <= "11";
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31 | when "11" => ANODE <= "0111";
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32 | seg7id <= "00";
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33 | digit := counter(15 downto 12);
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34 | when others => ANODE <= "1111";
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35 | seg7id <= "00";
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36 | end case;
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37 |
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38 | case digit is
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39 | when "0000" => SEG7 <= "00000011";
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40 | when "0001" => SEG7 <= "10011111";
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41 | when "0010" => SEG7 <= "00100101";
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42 | when "0011" => SEG7 <= "00001101";
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43 | when "0100" => SEG7 <= "10011001";
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44 | when "0101" => SEG7 <= "01001001";
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45 | when "0110" => SEG7 <= "01000001";
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46 | when "0111" => SEG7 <= "00011111";
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47 | when "1000" => SEG7 <= "00000001";
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48 | when "1001" => SEG7 <= "00001001";
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49 | when "1010" => SEG7 <= "00010011";
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50 | when "1011" => SEG7 <= "11100001";
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51 | when "1100" => SEG7 <= "11100101";
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52 | when "1101" => SEG7 <= "10000101";
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53 | when "1110" => SEG7 <= "11000001";
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54 | when "1111" => SEG7 <= "11100001";
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55 | when others => SEG7 <= "11111101";
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56 | end case;
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57 |
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58 | end if;
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59 | end process;
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60 |
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61 | end V1;
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Leider sehe ich auf der Anzeige nur 8888, wobei die richtigen Segmente
etwas kräftiger erscheinen.
Ich hatte auch versucht, den display-Prozeß zu teilen und digit zum
Signal zu machen, aber der Fehler blieb.
Kann mir jemand zeigen, was ich falsch mache? Oder ist der Takt zu hoch?