1 | -- Typ Board TEWS TCP630-10
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2 | -- Clock auf dem Board 200kHz - 166MHz
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3 |
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4 |
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5 | library ieee ;
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6 | use ieee.std_logic_1164.all;
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7 | use IEEE.std_logic_unsigned.all;
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8 | library GRLIB;
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9 | use grlib.amba.all;
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10 |
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11 | ENTITY register_rtc IS
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12 | generic(n: natural :=32;
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13 | m: natural :=16;
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14 | o: natural :=8);
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15 | PORT(clk, clk2, reset: in std_logic;
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16 | -- ahbso: out ahb_slv_out_type;
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17 | hresp: out std_logic_vector(1 downto 0);
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18 | hrdata: out std_logic_vector(31 downto 0);
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19 | hready: out std_ulogic;
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20 |
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21 | tmp_set_FTime: out std_logic_vector(m-1 downto 0); -- debug
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22 | tmp_FTime: out std_logic_vector(m-1 downto 0); -- debug
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23 | tmp_reg_ctrl : out std_logic_vector (o-1 downto 0); -- debug
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24 | tmp_ctr_haddr : out std_logic_vector (1 downto 0); -- debug
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25 | tmp_haddr_zwsp : out std_logic_vector(1 downto 0); -- debug
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26 | tmp_step1, tmp_step2, tmp_step3, tmp_step4, tmp_step5 : out std_logic; -- debug
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27 |
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28 | -- ahbsi: in ahb_slv_in_type --(Sel, Trans, Addr, Write, Size, Burst, Prot, Ready)
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29 | hsel: in std_logic_vector (0 to m-1);
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30 | haddr: in std_logic_vector(31 downto 0);
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31 | hwrite: in std_ulogic;
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32 | htrans: in std_logic_vector(1 downto 0);
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33 | hsize: in std_logic_vector(2 downto 0);
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34 | hburst: in std_logic_vector(2 downto 0);
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35 | hwdata: in std_logic_vector(31 downto 0);
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36 | hprot: in std_logic_vector(3 downto 0)
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37 | );
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38 | end register_rtc;
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39 |
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40 | architecture behv of register_rtc is
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41 |
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42 | type ctrl_type is record
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43 | htrans : std_logic_vector (1 downto 0);
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44 | haddr : std_logic_vector (1 downto 0);
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45 | hsize : std_logic_vector (2 downto 0);
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46 | hburst : std_logic_vector (2 downto 0);
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47 | hprot : std_logic_vector (3 downto 0);
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48 | hsel_rtc : std_logic_vector (0 to 15);
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49 | hwrite : std_ulogic;
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50 | hctrl : std_logic;
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51 | hrdata : std_logic;
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52 | hready : std_logic;
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53 | end record;
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54 |
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55 | type zwsp_type is record
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56 | htrans : std_logic_vector (1 downto 0);
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57 | haddr : std_logic_vector (1 downto 0);
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58 | hsize : std_logic_vector (2 downto 0);
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59 | hburst : std_logic_vector (2 downto 0);
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60 | hprot : std_logic_vector (3 downto 0);
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61 | hwrite : std_ulogic;
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62 | end record;
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63 |
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64 | signal Set_FTime, FTime: std_logic_vector(m-1 downto 0);
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65 | signal Set_CTime, CTime: std_logic_vector(n-1 downto 0);
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66 | signal Counter: std_logic_vector(o-1 downto 0);
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67 | signal reg_ctrl: std_logic_vector (o-1 downto 0); -- Controlregister
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68 | signal ctrl: ctrl_type;
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69 | signal zwsp: zwsp_type;
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70 | signal tmp_hrdata: std_logic_vector (n-1 downto 0);
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71 | signal speichern, gespeichert, phase, vormerker_ende, enduebertragung, readymerk, reset_signal: std_logic;
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72 |
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73 | begin
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74 |
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75 |
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76 | connect: process(clk2, hsel, ctrl.hready)
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77 | begin
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78 | if (reset = '1') then
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79 | ctrl.hsel_rtc <= "0000000000000000";
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80 | elsif (clk2 = '1' and clk2'event) then
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81 | if (clk = '1') then
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82 | if(hsel = "0000000000000001" and not ctrl.hready = '1') then
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83 | ctrl.hsel_rtc <= "0000000000000001";
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84 | else
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85 | ctrl.hsel_rtc <= "0000000000000000";
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86 | end if;
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87 | end if;
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88 | end if;
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89 | end process connect;
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90 |
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91 |
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92 | ctrl_p: process(clk2, ctrl.hsel_rtc, reset)
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93 | begin
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94 | if (reset = '1') then
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95 | ctrl.htrans <= (others =>'0');
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96 | ctrl.hsize <= (others =>'0');
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97 | ctrl.hburst <= (others =>'0');
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98 | ctrl.haddr <= (others =>'0');
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99 | ctrl.hwrite <= '0';
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100 | ctrl.hctrl <= '0';
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101 | speichern <= '0';
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102 | elsif (clk2'event and clk2 = '0') then
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103 | if(ctrl.hsel_rtc = "0000000000000001") then
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104 | case htrans is
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105 | when "01" => ctrl.htrans <= "01";
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106 | when "10" => ctrl.htrans <= "10";
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107 | when "11" => ctrl.htrans <= "11";
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108 | when others => ctrl.htrans <= "00"; -- Statusmeldung und Fehlerbehandlung
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109 | end case;
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110 |
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111 | case hsize is
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112 | when "000" => ctrl.hsize <= "000";
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113 | when "001" => ctrl.hsize <= "001";
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114 | when "010" => ctrl.hsize <= "010"; -- Word 32-bit
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115 | when "011" => ctrl.hsize <= "011";
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116 | when "100" => ctrl.hsize <= "100";
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117 | when others => ctrl.hsize <= "111";
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118 | end case;
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119 |
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120 | case hburst is
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121 | when "000" => ctrl.hburst <= "000"; -- single Mode
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122 | when "001" => ctrl.hburst <= "001";
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123 | when "010" => ctrl.hburst <= "010";
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124 | when "011" => ctrl.hburst <= "011";
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125 | when "100" => ctrl.hburst <= "100";
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126 | when others => ctrl.hburst <= "111";
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127 | end case;
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128 |
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129 | case haddr is
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130 | when "00000000000000000000000000000000" => ctrl.haddr <= "00"; -- Controlregister
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131 | when "00000000000000000000000000000001" => ctrl.haddr <= "01"; -- CTimeregister
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132 | when "00000000000000000000000000000010" => ctrl.haddr <= "10"; -- FTimeregister
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133 | when others => ctrl.haddr <= "11";
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134 | end case;
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135 |
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136 | ctrl.hwrite <= hwrite;
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137 | ctrl.hctrl <= '1';
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138 |
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139 | -- case ahbsi.hprot is
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140 | --irgendwann mal anfangen zu implementieren
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141 | -- end case;
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142 |
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143 | if (gespeichert = '0') then
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144 | speichern <= '1';
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145 | else
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146 | speichern <= '0';
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147 | end if;
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148 |
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149 | end if;
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150 | end if;
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151 | end process ctrl_p;
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152 |
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153 |
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154 | wert_zwsp: process (reset, ctrl.hsel_rtc, clk2)
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155 | begin
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156 | if (reset = '1' or ((phase = '1') and (ctrl.hsel_rtc = "0000000000000001")) ) then
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157 | zwsp.htrans <= (others =>'0');
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158 | zwsp.hsize <= (others =>'0');
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159 | zwsp.hburst <= (others =>'0');
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160 | zwsp.haddr <= (others =>'0');
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161 | zwsp.hwrite <= '0';
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162 | gespeichert <= '0';
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163 | elsif ((ctrl.hready = '0') and (hsel = "0000000000000001")) then
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164 | if (clk2='1' and clk2'event) then
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165 | if (speichern = '1') then
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166 | zwsp.htrans <= ctrl.htrans;
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167 | zwsp.hsize <= ctrl.hsize;
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168 | zwsp.hburst <= ctrl.hburst;
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169 | zwsp.haddr <= ctrl.haddr;
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170 | zwsp.hwrite <= ctrl.hwrite;
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171 | gespeichert <= '1';
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172 | else
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173 | gespeichert <= '0';
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174 | end if;
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175 | end if;
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176 | end if;
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177 | end process wert_zwsp;
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178 |
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179 |
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180 | lesen: process(reset, hwrite, phase, reset_signal)
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181 | begin
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182 | if ((reset = '1') or (reset_signal = '1')) then
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183 | tmp_hrdata <= (others =>'0');
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184 | ctrl.hrdata <= '0';
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185 | elsif (hwrite = '0' and phase = '1') then
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186 | ctrl.hrdata <= '1';
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187 | if (zwsp.haddr = "01") then
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188 | tmp_hrdata <= CTime;
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189 | elsif (zwsp.haddr = "10") then
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190 | tmp_hrdata (15 downto 0) <= FTime;
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191 | tmp_hrdata (n-1 downto 16) <= (others =>'0');
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192 | elsif (zwsp.haddr = "00") then
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193 | tmp_hrdata (o-1 downto 0) <= reg_ctrl;
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194 | tmp_hrdata (n-1 downto o) <=(others =>'0');
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195 | end if;
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196 | end if;
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197 | end process lesen;
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198 |
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199 |
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200 | phasen: process (gespeichert, clk, reset_signal)
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201 | begin
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202 | if (clk = '1' and clk'event) then
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203 | if(gespeichert = '1' and not (reset_signal = '1')) then
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204 | phase <= '1'; --Datenphase
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205 | else
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206 | phase <= '0'; --Adressphase
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207 | end if;
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208 | end if;
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209 | end process phasen;
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210 |
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211 |
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212 | ready: process (enduebertragung, readymerk)
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213 | begin
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214 | if (reset = '1') or (enduebertragung = '1') then
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215 | ctrl.hready <= '0';
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216 | elsif (readymerk = '1') then
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217 | ctrl.hready <= '1';
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218 | end if;
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219 | end process ready;
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220 |
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221 |
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222 | start_ready: process (clk2, reset, Phase)
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223 | begin
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224 | if (reset = '1') or (enduebertragung = '1') then
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225 | readymerk <= '0';
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226 | elsif ((clk2 = '1' and clk2'event) and (Phase = '1')) then
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227 | readymerk <= '1';
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228 | end if;
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229 | end process start_ready;
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230 |
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231 |
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232 | ende: process (clk, reset, vormerker_ende, reset_signal)
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233 | begin
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234 | if ((reset = '1') or (reset_signal = '1')) then
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235 | enduebertragung <= '0';
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236 | elsif ((clk = '1' and clk'event) and (vormerker_ende = '1')) then
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237 | enduebertragung <= '1';
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238 | end if;
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239 | end process ende;
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240 |
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241 |
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242 | ruecksetzen: process (enduebertragung)
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243 | begin
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244 | case enduebertragung is
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245 | when '1' =>
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246 | reset_signal <= '1';
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247 | when others =>
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248 | reset_signal <= '0';
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249 | end case;
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250 | end process ruecksetzen;
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251 |
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252 |
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253 | response: process (clk, phase, reset_signal) -- noch zu Ergänzen
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254 | begin
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255 | if ((reset = '1') or (reset_signal = '1')) then
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256 | hresp <= "11"; --noch zu aendern
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257 | vormerker_ende <= '0';
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258 | elsif ((clk'event and clk = '0') and (phase = '1')) then
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259 | hresp <= "00"; --Statusmeldung
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260 | vormerker_ende <= '1';
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261 | end if;
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262 | end process response;
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263 |
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264 |
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265 | schreiben: process (reset, clk2)
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266 | begin
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267 | if (reset = '1') then
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268 | set_CTime <= (others =>'0');
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269 | set_FTime <=(others =>'0');
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270 | tmp_set_FTime <=(others =>'0');
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271 | reg_ctrl <= (others =>'0');
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272 | tmp_step1 <= '0';
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273 | elsif(clk2 = '1' and clk2'event) then
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274 | if (zwsp.hwrite = '1' and phase = '1') then
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275 | if (zwsp.haddr = "01") then
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276 | set_CTime <= hwdata;
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277 | elsif (zwsp.haddr = "10") then
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278 | set_FTime <= hwdata (m-1 downto 0);
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279 | tmp_set_FTime <= set_FTime;
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280 | tmp_step1 <= '1';
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281 | elsif (zwsp.haddr = "00") then
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282 | reg_ctrl <= hwdata(o-1 downto 0);
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283 | end if;
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284 | end if;
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285 | end if;
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286 | end process schreiben;
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287 |
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288 |
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289 | -- 200 kHz -> 0.005 ms -> 1100 0111 fuer Counter
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290 | count: process(clk, reset)
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291 | begin
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292 | if (reset = '1') then
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293 | FTime <= (others =>'0');
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294 | CTime <= (others =>'0');
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295 | Counter <= (others =>'0');
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296 | tmp_FTime <= (others =>'0');
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297 | tmp_step2 <= '0';
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298 | elsif (reg_ctrl(0) = '1') then
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299 | FTime <= set_FTime;
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300 | CTime <= set_CTime;
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301 | Counter <=(others =>'0');
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302 | tmp_step2 <= '1';
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303 | elsif (clk='1' and clk'event) then
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304 | if (reg_ctrl = "00000010") then
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305 | Counter <= Counter + 1;
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306 | if Counter = "00000011" then
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307 | FTime <= FTime + 1;
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308 | tmp_FTime <= FTime;
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309 | Counter <=(others =>'0');
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310 | if FTime = "0000000000000111" then
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311 | CTime <= CTime + 1;
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312 | FTime <= (others =>'0');
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313 | Counter <= (others =>'0');
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314 | end if;
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315 | end if;
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316 | end if;
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317 | end if;
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318 | end process count;
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319 |
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320 | hready <= ctrl.hready;
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321 | hrdata <= tmp_hrdata;
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322 |
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323 | tmp_reg_ctrl <= reg_ctrl;
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324 | tmp_haddr_zwsp <= zwsp.haddr;
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325 | end behv;
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