Suchergebnisse für "when others"

Datei

user_logic.vhd

) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); else case slv_reg_write_sel is when "100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then

in „[VHDL] Mappen von Ports klappt nicht“ · FPGA, VHDL & Co. · 01.06.2010 14:52

Datei

dso.vhd

NEXTSTATE <= RESET_ADR; end if; when RESET_ADR => NEXTSTATE <= IDLE; when others => NEXTSTATE <= IDLE; end case; end process; --clock-ausgang für den ad-wandler: invertiert, da bei steigender taktflanke ein neuer --wert ausgegeben wird

in „Zähler aus zwei Clock-Quellen speisen“ · FPGA, VHDL & Co. · 20.02.2008 23:48

Datei

FSMTest.vhd

cpuClk'event AND cpuClk = '1' THEN IF cpuRst = '1' THEN intMemEn <= '0'; intMemWe <= '0'; adReg <= (OTHERS => '0'); intMemDataOut <= (OTHERS => '0'); state <= STPutW0; ELSE CASE state IS WHEN STPutW0 => adReg <= o"0014"; intMemDataOut <= o"1111"; intMemEn <= '1'; intMemWe <= '1'; state <= STPutW1; WHEN

in „VHDL Zugriff FSM auf Speicher“ · FPGA, VHDL & Co. · 20.08.2012 12:01

Datei

Neuron.vhd

Add_invalid_op, rdy => Add_rdy ); process begin wait until rising_edge(clk); if(reset = '1') then Add_sum <= (others => '0'); Mult_a <= (others => '0'); Mult_b <= (others => '0'); int_Output <= (others => '0'); int_ready <= '1'; Neuron_state <= idle; counter <= 0; else case Neuron_state is when idle => if(execute

in „Pipeline MAC-Unit: Problem mit Latency“ · FPGA, VHDL & Co. · 09.04.2026 16:35

Datei

sr_adc5.vhdl

process serial data counter process (cs, o_clock, scounter) begin if (cs = '0') then acounter <= (others=>'0'); nWE <= '1'; elsif rising_edge(o_clock) then case scounter is when "000000" => -- 0 aconv <= '1'; when "000010" => -- 2 aconv <= '0'; when "011111" => -- 31 acounter <= std_logic_vector(unsigned

in „Der vhdl-Schnipsel-Anfängerfragen Thread“ · FPGA, VHDL & Co. · 26.07.2009 14:47

Datei

crtc.vhd

(fifo_rp)); fifo_rp <= fifo_rp + 1; end if; end process; -- drive sync signals vga_hs <= '0' when hcount < mode(1) else '1' when hcount < mode(2) else '0'; vga_vs <= '0' when vcount < mode(5) else '1' when vcount < mode(6) else '0'; -- drive pixel data visible <= '1' when (hcount < mode(0) and vcount < mode(4)) else '0'; vga_r <= pixel(15 downto 11) when visible = '1' else (others => '0'); vga_g <= pixel(10 downto 5) when visible = '1' else (others => '0'); vga_b <= pixel( 4 downto 0) when visible = '1' else (others => '0'); -- fifo state fifo_full

in „Frame-Synchronisierung für VGA“ · FPGA, VHDL & Co. · 19.06.2018 19:27

Datei

user_logic.vhd

) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); --slv_reg2 <= (others => '0'); else case slv_reg_write_sel is when "100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then

in „Eigenen Code sauber in PLB Slave Template einbinden“ · FPGA, VHDL & Co. · 19.08.2010 10:18

Datei

user_logic.vhd

) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); else case slv_reg_write_sel is when "100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then

in „startan 3e starte kit, DAC in C in SDK“ · FPGA, VHDL & Co. · 05.07.2010 21:44

Datei

user_logic.vhd

) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); else case slv_reg_write_sel is when "100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then

in „spartan 3e starter kit, DAC in C in SDK“ · FPGA, VHDL & Co. · 05.07.2010 23:44

Datei

user_logic.vhd

) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); else case slv_reg_write_sel is when "100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then

in „Slaveregister in SDK“ · FPGA, VHDL & Co. · 15.07.2010 19:47

Datei

regf_decoder.vhd

regf_decoder; architecture behaviour of regf_decoder is begin process(NUMBER) begin R_DECODE <= (others => '0'); case NUMBER is when "00000" => R_DECODE(0) <= '1'; when "00001" => R_DECODE(1) <= '1'; when "00010" => R_DECODE(2) <= '1'; when "00011" => R_DECODE(3) <= '1'; when "00100" => R_DECODE(4) <

in „Registerspeicher“ · FPGA, VHDL & Co. · 22.05.2011 19:52

Datei

sram_spi_code_vhdl.txt

<= (others => '0'); sram_data <= (others => 'Z'); --sram_data als Eingang unsigned_ce_addr <= "1110"; unsigned_sram_data <= (others => '0'); sig_Reset <= not sig_Reset; end if; when "001" => -- LESEVORGANG if

in „SRAM SPI Tristate Problem“ · FPGA, VHDL & Co. · 16.08.2008 15:45

Datei

Code.txt

counter2 + 1; --alle 240ms wird der counter1 zurückgesetzt if counter1 = 24000 then counter1 <=(others =>'0'); end if; end if; --Counter reset if int_reset = '1' then counter1 <= (others =>'0'); counter2 <= (others =>'0'); flag_empfang1 <= '0'; flag_empfang2 <= '0'; end if; int_reset <='0'; --wird ein

in „Tri-State ausgänge (XC95144XL)“ · FPGA, VHDL & Co. · 18.10.2012 17:30

Datei

uart_rx.vhd

state_reg; s_next <= s_reg; n_next <= n_reg; b_next <= b_reg; rx_done_tick <='0'; case state_reg is when idle => if rx='0' then state_next <= start; s_next <= (others=>'0'); end if; when start => if (s_tick = '1') then if s_reg=7 then state_next <= data; s_next <= (others=>'0'); n_next <= (others=>'0'); else s_next <= s_reg + 1; end if; end if; when data => if (s_tick = '1') then if s_reg=15 then s_next <= (others=>'0'); b_next <= rx & b_reg(7 downto 1) ; if n_reg=(DBIT-1) then state_next <= stop ; else n_next <= n_reg + 1; end if; else s_next

in „UART Test Hilfe!“ · FPGA, VHDL & Co. · 11.05.2010 11:39

Datei

arctanFP.vhd

3:= 0; BEGIN IF rising_edge(clk) THEN IF nrst = '0' THEN stateatan <= 0; ce1 <= '0'; --InpA <= (OTHERS => '0'); ---InpB <= (OTHERS => '0'); cntrclk := 0; --(OTHERS => '0'); ELSE CASE stateatan IS WHEN 0 => IF ceatan = '1' THEN stateatan <= 1; --InpA <= Xinp; --InpB <= Yinp; cntrclk := 1;-- time for

in „Post-Map simulation mit ModelSim“ · FPGA, VHDL & Co. · 07.09.2024 11:38

Datei

uart_tx.vhd

s_reg; n_next <= n_reg; b_next <= b_reg; tx_next <= tx_reg ; tx_done_tick <= '0'; case state_reg is when idle => tx_next <= '1'; if tx_start='1' then state_next <= start; s_next <= (others=>'0'); b_next <= din; end if; when start => tx_next <= '0'; if (s_tick = '1') then if s_reg=15 then state_next <= data; s_next <= (others=>'0'); n_next <= (others=>'0'); else s_next <= s_reg + 1; end if; end if; when data => tx_next <= b_reg(0); if (s_tick = '1') then if s_reg=15 then s_next <= (others=>'0'); b_next <= '0' & b_reg(7

in „UART Test Hilfe!“ · FPGA, VHDL & Co. · 11.05.2010 11:39

Datei

counter.vhd

std_logic_vector(31 downto 0); begin process(clk) begin if rising_edge(clk) then if reset = '1' then q <= (others => '0'); count <= (others => '0'); else if count = x"FFFFFFFF" then count <= (others => '0'); else count <= count +1; end if; case switches is when "0001" => q <= count(7 downto 0); when "0010" => q <= count(15 downto 8); when "0100" => q <= count(23 downto 16); when "1000" => q <= count(31 downto 24); when others => q <= (others => '0'); end case; end if; end if; end process; end Behavioral;

in „LED-Zähler mit Xilinx CPLD“ · FPGA, VHDL & Co. · 12.10.2006 05:59

Datei

counter.vhd

std_logic_vector(31 downto 0); begin process(clk) begin if rising_edge(clk) then if reset = '1' then q <= (others => '0'); count <= (others => '0'); else if enable = '0' then -- if count = x"FFFFFFFF" then --Counter anuell resetten... -- count <= (others => '0'); --else count <= count +1; --end if; end if; case switches is when "0001" => q <= count(7 downto 0); when "0010" => q <= count(15 downto 8); when "0100" => q <= count(23 downto 16); when "1000" => q <= count(31 downto 24); when others => q <= (others => 'Z'); --Schaltet

in „LED-Zähler mit Xilinx CPLD“ · FPGA, VHDL & Co. · 12.10.2006 05:59

Datei

Display.vhd

", -- 8 "0010000" when "1001", -- 9 "0001000" when "1010", -- A "0000011" when "1011", -- B "1000110" when "1100", -- C "0100001" when "1101", -- D "0000110" when "1110", -- E "0001110" when "1111", -- F "1000000" when others

in „Binär zu BCD wandlung“ · FPGA, VHDL & Co. · 27.05.2013 18:28

Datei

user_logic.vhd

, slv_reg1 ) is begin case slv_reg_read_sel is when "10" => slv_ip2bus_data <= slv_reg0; when "01" => slv_ip2bus_data <= slv_reg1_1 or slv_reg1_2;--slv_reg1; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC

in „Custom IP-Core für Mittelwert/Standardabweichung“ · FPGA, VHDL & Co. · 26.05.2011 08:52

Datei

generator.txt

0; when 61 => return 0; when 62 => return 0; when 63 => return 0; when others => return 0; end case; end function sinus; begin function_generator: process(clk10) variable prescaler: std_logic_vector(7 downto

in „VHDL-Typenkonvertierung“ · FPGA, VHDL & Co. · 11.10.2006 23:49

Datei

DISPLAY.vhd

std_logic); end Broke; architecture verhalten of Broke is begin with cardsum select broke <= '1' when "10110", '1' when "10111", '1' when "11000", '1' when "11001", '1' when "11010", '1' when "11011", '1' when "11100", '1' when "11101", '1' when "11110", '1' when "11111", '0'when others; end verhalten

in „Rechnen mit signed und unsigned“ · FPGA, VHDL & Co. · 20.04.2010 18:59

Datei

Neuron_tb.vhd

downto 0) := (others => '0'); signal Mem_Data_In : std_logic_vector(15 downto 0) := (others => '0'); signal Input : std_logic_vector(15 downto 0) := (others => '0'); signal Address : std_logic_vector(6 downto 0) := (others

in „Pipeline MAC-Unit: Problem mit Latency“ · FPGA, VHDL & Co. · 07.04.2026 11:00

PDF

lab10.pdf

<= S0; case (state) is when S0 => if (x = '1') then next_state <= S1; end if; when S1 => if (x = '0') then next_state <= S1; end if; when others => next_state <= S0; end case; end process; The state assignments can be of one-hot

in „Probleme bei Vivado Tutorial mit State Machine“ · FPGA, VHDL & Co. · 28.03.2021 18:17

Datei

Quicksort.vhd

increment : process (clock_quicksort) begin if falling_edge (clock_quicksort) then case state is when idle_state => read_address_quicksort_internal <= (others => '0'); write_address_quicksort_internal <= (others => '0'); state <= data_in_state; when data_in_state => write_address_quicksort_internal

in „hinder the constant cleaning in the block“ · FPGA, VHDL & Co. · 09.08.2008 14:37

Datei

sieben_segment.vhd

segm<="1100000"; -- b -- WHEN "1100"=>segm<="0110001"; -- C -- WHEN "1101"=>segm<="1000010"; -- d -- WHEN "1110"=>segm<="0010000"; -- E -- WHEN "1111"=>segm<="0111000"; -- F -- WHEN OTHERS=>segm<="0000000"; -- mögliche andere Fälle

in „Fehler im VHDL-Quellcode“ · FPGA, VHDL & Co. · 10.11.2009 09:57

Datei

IO_mux.vhd

signal adr_int : integer; begin adr_int <= conv_integer(adr_bus); -- IO read mux data_bus <= read_bus when rd = '0' and cs = '0' else (others=>'Z'); -- register write access process(wr) begin if rising_edge(wr) then if cs='0' then my_reg(adr_int) <= data_bus; end if; end if; end process; -- register read

in „VHDL: Multiplexer mit generischer Anzahl zu muxender Busse?“ · FPGA, VHDL & Co. · 14.12.2006 09:13

Datei

data_to_bram.vhd

downto 0) <= rx_data_in; when 3 => k2_i(15 downto 8) <= rx_data_in; when 4 => p1_i(7 downto 0) <= rx_data_in; when 5 => p1_i(15 downto 8) <= rx_data_in; when 6 => p2_i(7 downto 0) <= rx_data_in; when 7 => p2_i(15 downto 8) <= rx_data_in; when 8 => fx_i(7 downto 0) <= rx_data_in; when 9 => fx_i(15 downto 8) <= rx_data_in; when 10 => fy_i(7 downto 0) <= rx_data_in; when 11 => fy_i(15 downto 8) <= rx_data_in; when 12 => cx_i(7 downto 0) <=

in „Ethernet Problem“ · FPGA, VHDL & Co. · 12.01.2010 14:58

Datei

calc.vhd

downto 0); variable e2: std_logic_vector(39 downto 0); begin next_state <= state; case (state) is when st0_idle => next_state <= st0_idle; when st1_calc1 => mu1_a <= num1; mu1_b <= num2; next_state <= st2_calc2; when st2_calc2 => result12 <= mu1_product; next_state <= st3_calc3; when st3_calc3 => mu1_a <= num3; mu1_b <= num4; next_state <= st4_calc4; when st4_calc4 => result34 <= mu1_product; next_state <= st5_calc5; when st5_calc5 => result <= result12 + result34; next_state <= st6_idle; when st6_idle => next_state <= st6_idle; when others => next_state

in „Latch bei Berechnung mittels FSM“ · FPGA, VHDL & Co. · 25.11.2008 16:17

Datei

IO_mux.vhd

integer range 0 to 15; begin adr_int <= conv_integer(adr_bus); -- IO read mux data_bus <= read_bus when rd = '0' and cs = '0' else (others=>'Z'); -- register write access process(wr) begin if rising_edge(wr) then if cs='0' then my_reg(adr_int) <= data_bus; end if; end if; end process; -- register read

in „VHDL: Multiplexer mit generischer Anzahl zu muxender Busse?“ · FPGA, VHDL & Co. · 14.12.2006 10:16

PDF

P20101.pdf

VCC_C becomes lower than VDD whenever VDD, VDDIO is ON and VCC_C is OFF. VCC_C should be disabled when it is OFF. - 15 - REV.: X02 2008/03/20 This document contains confidential and proprietary inNeither it nor the information contained herein shall be disclosed to others or duplicated or used for others

in „RiTdisplay - Ansteuerung“ · Mikrocontroller und Digitale Elektronik · 11.09.2008 16:02

Datei

HMCAD1511.vhd

:=(others => '0'); signal Byte_Serdes_4: std_logic_vector(7 downto 0):=(others => '0'); signal Byte_Serdes_5: std_logic_vector(7 downto 0):=(others => '0'); signal Byte_Serdes_6: std_logic_vector(7 downto 0):=(others => '0'); signal Byte_Serdes_7: std_logic_vector(7 downto 0):=(others => '0'); signal Byte_Serdes_FCLK: std_logic_vector(7 downto 0):=(others => '0'); signal TwoByte_Serdes_0: std_logic_vector(15 downto

in „HMCAD1511 Interface“ · FPGA, VHDL & Co. · 15.08.2020 00:56

PDF

AA51880.pdf

ELECTRICAL CHARACTERISTICS Ta=25℃, Vcc=4.8V LIMITS SYMBOL PARAMETER TEST CONDITIONS UNIT MIN TYP MAX When output is OFF - 5 8 mA ICC Operating current When output is ON - 25 28 mA VOL Output voltage "L" Load resistor 20Ω - 0.1 0.2 V VOH Output voltage "H" Load resistor 240Ω 3.5 - - V External PNP transistor

in „Servo-Elektronik mit AA51880 Controller zerstört sich selbst“ · Analoge Elektronik und Schaltungstechnik · 26.10.2021 14:21

PDF

AA51880.pdf

ELECTRICAL CHARACTERISTICS Ta=25℃, Vcc=4.8V LIMITS SYMBOL PARAMETER TEST CONDITIONS UNIT MIN TYP MAX When output is OFF - 5 8 mA ICC Operating current When output is ON - 25 28 mA VOL Output voltage "L" Load resistor 20Ω - 0.1 0.2 V VOH Output voltage "H" Load resistor 240Ω 3.5 - - V External PNP transistor

in „Servo-Elektronik mit AA51880 Controller zerstört sich selbst“ · Analoge Elektronik und Schaltungstechnik · 27.10.2021 18:16

Datei

fbas_enc.vhd

" => vout <= "00110"; when "011" => vout <= "01000"; when "100" => vout <= "01011"; when "101" => vout <= "01101"; when "110" => vout <= "01011"; when "111" => vout <= "01000"; when others => vout <= "01000"; end case; else case

in „Video-Farbausgabe mit ATmega88“ · Mikrocontroller und Digitale Elektronik · 20.02.2007 19:42

Datei

interface.vhd

RST) begin if RST = '0' then cnt <= 0; elsif CLK_PLL = '1' and CLK_PLL'event then case state is --when GAIN_SWITCH => cnt <= 0; when CONFIG_1 => cnt <= 0; when CONFIG_2 => cnt <= 0; when CONFIG_3 => cnt <= 0; when CH_SEL => cnt <= 0; when START => if cnt < 4 then cnt <= cnt + 1; elsif cnt >= 4 and rts_master_ar_s

in „Sehr seltsames Verhalten eines VHDL-Designs, Bitte um Hilfe“ · FPGA, VHDL & Co. · 01.03.2012 08:18

Datei

Neuron.vhd

<= count_in + 1; if(count_in = INPUTS-1) then count_wait <= 0; Neuron_state <= pipe; Mult_a <= (others => '0'); Mult_b <= (others => '0'); end if; when pipe => Add_sum <= Add_result; count_wait <= count_wait + 1; if(count_wait = (2*LATENCY)-1) then Neuron_state <= finish; end if; when finish => int_Output <= Add_result; if(execute = '0') then Neuron_state <= idle; end if; when others => Neuron_state <= idle; end case; end if; end process; Output <= int_Output; Weight_Adr <= Layer_page & Layer_Input_Number; ready <= int_ready and not(execute); error <= Mult_underflow or Mult_overflow

in „Pipeline MAC-Unit: Problem mit Latency“ · FPGA, VHDL & Co. · 03.04.2026 19:50

Datei

frameerzeuger.vhd

<= '1' when sig_count_tx_data = "0000" else '0'; sig_tx_data_register <= "00000011" when sig_send_bof = '1' else "10000011" when sig_send_eof = '1' else TX_FIFO_DATA_IN; --DATA_IO <= sig_tx_data_register; --sig_tx_fifo_empty

in „INOUT Port - Richtung umschalten“ · FPGA, VHDL & Co. · 30.01.2008 17:32

Datei

i2s_in.vhd

: process (sclk_in, nreset) begin if nreset='0' then state_reg <= idle; right_reg <= (0 => '1', others => '0'); left_reg <= (0 => '1', others => '0'); ready <= '0'; else if rising_edge(sclk_in) then state_reg <= state_reg; case state_reg is when idle => ready <= '0'; if falling_edge(lrck_in) then state_reg

in „von langsamer in schnellere taktdomain“ · FPGA, VHDL & Co. · 03.12.2013 18:52

Datei

ddr.vhd

time tWR: 15 ns when RecoverWrite => min.cmd <= CMD_NOP; min.ba <= "00"; min.adr(10) <= '0'; min.adr(9 downto 1) <= (others => '0'); if m.c = 1 then min.c <= 0; min.s <= PrechargeWait; else min.c <= m.c + 1; end if; ---

in „Spartan-3E Starter Kit + DDR2“ · FPGA, VHDL & Co. · 22.04.2012 15:08

Datei

fifo.vhd

w_ptr_reg; r_ptr_next <= r_ptr_reg; full_next <= full_reg; empty_next <= empty_reg; case wr_op is when "00" => -- no op when "01" => -- read if (empty_reg /= '1') then -- not empty r_ptr_next <= r_ptr_succ; full_next <= '0'; if (r_ptr_succ=w_ptr_reg) then empty_next <='1'; end if; end if; when "10" =

in „UART Test Hilfe!“ · FPGA, VHDL & Co. · 11.05.2010 11:38

Datei

bsp.txt

Bsp.: CASE p1 IS WHEN "00000" => y <= '0'; WHEN "10000" => IF x >= z THEN y <= '1'; ELSE y <= '0'; END IF; WHEN OTHERS => y <= '0'; END CASE; Bsp.1: CASE p1 IS WHEN "00000" => y <= '0'; WHEN "10000" => IF x >= z THEN y <= '1'; ELSE y <= '0'; END IF; WHEN OTHERS => y <= '0'; END CASE; Bsp.2: y <= '0' CASE p1 IS WHEN "00000" => NULL; WHEN "10000" => IF x >= z THEN y <= '1'; END IF; WHEN OTHERS => NULL; END CASE;

in „if innerhalb case?“ · FPGA, VHDL & Co. · 11.10.2006 23:51

Datei

VERSION_REGISTER.vhd

ZERO) then -- if no CS for CPLD active, set Databus to high Z DATA <= (others =>'Z'); elsif (nRD'EVENT and nRD='0') then case CS is when (SHIFT_PATTERN sll START_CS_NR) => DATA <= CONV_STD_LOGIC_VECTOR(CPLD_VER, 8);--CPLD version register when (SHIFT_PATTERN sll (START_CS_NR +1))=> DATA <= CONV_STD_LOGIC_VECTOR(HW_VER, 8);--HW version register when (SHIFT_PATTERN sll (START_CS_NR +2))=> DATA <= CONV_STD_LOGIC_VECTOR(HW_TYPE, 8);--HW type register when others => DATA <= (others =>'Z'); end case; end if; end process; end BEHAVIOR;

in „VHDL: case problem Quartus 9.0 <-> ModelSim“ · FPGA, VHDL & Co. · 08.05.2009 07:33

Datei

prob.vhd

write_counter > 100) then write_enable <= '0'; end if; end if; end Process; --b_puffer <= puffer(0) when read_enable = '1'; -- Simulation --Buffer_VAL <= puffer(write_counter) when read_enable = '1' else (others => '0'); -- Hardware DRAM Buffer_VAL <= "001001010110101000001101111111100011111000000000000000000000000001011010" when read_enable = '1' else (others => '0'); full_loc <= '1' when (write_counter = 100) else '0'; Full <= full_loc; -- dafür, ob RAM voll ist end Behavioral;

in „ADC auslesen“ · FPGA, VHDL & Co. · 22.05.2014 16:23

Datei

mmb.vhd

CS2 SRAM 011 CS_Latch <= "011"; if AVR_AH(7 downto 2) = "000001" then case AVR_AH(1 downto 0) is when "01" => CS_Latch <= "111"; when "10" => CS_Latch <= "110"; when "11" => CS_Latch <= "101"; when others => NULL; end case; end if; end if; end process; process(AVR_WR, AVR_RD, AVR_AD, CS_Latch, Bank_Register

in „128kByte Ram an AVR“ · Mikrocontroller und Digitale Elektronik · 11.10.2006 16:56

Datei

MulAddSM.vhd

getaktet. process begin wait until rising_edge(clk); -- spart die Sensitivity-List case (state) is when st0_idle => if (num1 /= (others=>'0') ) then state <= st0_idle; end if; when st1_calc1 => mu1_a <= num1; mu1_b <= num2; state <= st2_calc2; when st2_calc2 => result12 <= mu1_product; state <= st3_calc3; when st3_calc3 => mu1_a <= num3; mu1_b <= num4; state <= st4_calc4; when st4_calc4 => result34 <= mu1_product; state <= st5_calc5; when st5_calc5 => result <= result12 + result34; state <= st0_idle; end

in „Latch bei Berechnung mittels FSM“ · FPGA, VHDL & Co. · 25.11.2008 16:40

Datei

ALU.txt

port map (not a, b, '1', nicht_a_minus_b (n-1 downto 0), nicht_a_minus_b (n)); with s select z1 <= (others => '0') when "0000", '0' & a when "0001", '0' & b when "0010", a_negativ when "0011", b_negativ when "0100", '0' & (not a) when "0101", '0' & (not b) when "0110", a_plus_b when "0111", a_minus_b when "1000", b_minus_a when "1001", nicht_a_minus_b when "1010", '0' & (a or b) when "1011", '0' & (a and b) when "1100", '0' & (a xor b) when "1101", '0' & (not (a xor b)) when "1110", (others => '1') when others; cout <= z1(

in „Einbinden mit component geht nicht.“ · FPGA, VHDL & Co. · 28.08.2008 23:50

Datei

fsm.vhd

S15 => count <= "1111"; if ain = '1' then yout <= '1'; else yout <= '0'; end if; when others => count <= "0000"; end case; end process; next_state_decode : process(state, ain) begin case(state) is when S0 => if ain = '1' then next_state <= S1; else next_state <= state; end if; when S1

in „Probleme bei Vivado Tutorial mit State Machine“ · FPGA, VHDL & Co. · 02.04.2021 13:57

Datei

NPI_Interface.vhd

; end if; when wait_for_falling => if (V_Sync_VideoIn = '0') then state_Set_WrAddrOffset <= wait_for_rising; end if; when others => state_Set_WrAddrOffset <= wait_for_rising; end case; end if; end process; -- Count

in „ChipScope problem“ · FPGA, VHDL & Co. · 16.11.2009 15:33

Datei

LA.vhd

idle; signal dly : integer range 0 to 15 := 0; signal start_sr : std_logic_vector (3 downto 0) := (others=>'0'); signal result : std_logic_vector (3 downto 0) := (others=>'0'); begin -- Startknopf eintakten start_sr <= start_sr(2 downto 0)&START when rising_edge(CLK); process begin wait until rising_edge

in „VHDL Verzögerung in process“ · FPGA, VHDL & Co. · 16.05.2019 14:43

Suchergebnisse für "when others"

2977 Treffer für when others Suchergebnisse für "when others"

2977 Treffer für when others