nRF54LS05 DK
Current measurement pins
User-programmable Debug in LEDs
Power switch
nPM1300 PMIC
GPIO pins shown in parentheses are only available on headers with modification
LED1 LED2 LED3
DEBUG IN
SWF RF port for direct RF measurements
2.4 GHz PCB Antenna
nRF54LS05 SoC
PCA10214
02.0
20.4
1052174718
SEGGER J-LINK
USB-C connector
DEBUGGER
Reset button
Debug out
SEGGER J-Link OB Programmer/debugger
BUTTON0 BUTTON 1
BUTTON 2 BUTTON 3
User-programmable buttons
cK1 $9 Q2 _ Gk Dk yHus us f$—-— —-— ta — —-— —— —— MK? st on Ti. -= | 1S7 10 5uLSOb 81 BP aa a2 3 54LS 139 7 6 ; ; ta R75 wu BIE Wag & 4 Hi | Sas An yo yi Y2 nea 560 uous a2) 6 Ab {i8 Q i PB - 1S04 7 1764/2732 as (2 8 pal A2 Ag = 1a2b| At ir 2 FrCHNwWRrUAMA 10 AO 00 01 07 03 4 05 05 o7_U% Fal nn[2 jo
, Lüfter, Außensteckdose 9 LS 16 A B
10 Bad: Licht, Steckdosen, Treppen-Licht, Boden 10 LS 16 A B
11 - 11 -
12 - 12 -
13 Geschirrspüler 13 LS 16 A B
14 Heizung Was bedeutet das "x"? 14 LS 16 A B
15 Küche: Licht, Steckdosen, Waschmaschine
Überstrom‐Schutzein- dem Zählerschrank zum Abb. 3: FI-Schutzschalter mit seschaltern zu den Stromkrei- 1-poligen LS-Schaltern richtungen für Beleuchtungs‐ Ladeplatz oder mindes- sen ist also zu beachten, und Steckdosenstromkreise tens ein entsprechendes dass das Abschalten eines sind LS-Schalter oder Elektroinstallationsrohr
in d e r 2 -p o l. 08 gn LV 7 -p o l. LS 1 09 b r LV 7 -p o l. LS 2 10 b l LV 7 -p o l. LS 3 11 g r LV 7 -p o l. LS 4 12 g r LV 7 -p o l. LS 5 13 SW LV 7 -p o l. LS 6 t', 14 sw LV 7 -p o l. LS 7 V15 r t Buchse p lu s Ls 22 Vl6 b l Buchse O V LS 25 17 b lan k LS 18 LS 21 e n t f ä l l t v18 gn LED+ LS 08 V19 g e r t LED - LS 09 J2o b rg e P2 1 LS 10 v21 grsw P2 2 LS 11 1122 wsge P2 3 LS 12 v23 rtsw PI 3 LS 15 v24 g r r t P l 2 LS 14 '25 v i
Bausatzkomplrtt. . .. nurDlVl60,- passendes SteakernelEeil .. nur DM 12,- 1*,1:":: f.'----i Labor-Netzgerdt NTL 05 den €rlolgroichen Funklionsgenerator nach eMeiterlunddadurch noch vielseiliger 0,0-50 v, o-.3 A und f Hiormit stellen wir phantastlschen aKo Aulbau - 2 hochwerligeModule in attrakilvem,Styllng!Besondere
= 2.500DC 1 LSB 3 2 RIN V REF/2 input resistance VCC = 0V 400 680 3 Analog input voltage range –0.05 V CC+0.05 V Over analog input voltage DC common-mode error 1/16 1/8 LSB range 1 Power supply sensitivity VCC = 5V 〉 10% 1/16 LSB Control inputs VIH Logical “1” input voltage VCC = 5.25DC 2.0 15 V DC
Gitterstrom der 1. Röhre und durch die Wirkung der natür- 1 ) L e tz ts te d e n ufü r W e c h s e ls tr o m n e tz a n s c h lu ß b e s tim m te n , s o n s t aber gleichen Empfänger VE 301W dar. a) Hochfrequenzteil 243 liehen Gitteranodenkapazität (vgl. später) auf etwa den 10. bis 20. Teil vermindern
−0.3V to (CC +0.3V) ADC0804LCJ −40˚C≤T A+85˚C C 0 Lead Temp. (Soldering, 10 seconds) ADC0801/02/03/05LCN −40˚C≤T A≤+85˚C 8 Dual-In-Line Package (plastic) 260˚C ADC0804LCN 0˚C≤TA≤+70˚C 3 Dual-In-Line Package (ceramic) 300˚C A ADC0802/04LCWM 0˚C≤TA≤+70˚C D Surface Mount Package Range of VCC 4.5 VDC to
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S ST9 G SMD A1 R21 BC858 120 SMD D D D 12V 2A SMD +5V S S S ST10 D2 +5V Q1 1 IC6 3 R 7 R 7 R 7 78L05 IC2 D 4,194304 +5V 4 4 4 1N4001 1 A1 VCC 8 R 0 M 2 A2 Test 7 1 S 1 MHz 230V~ 2 3 A3 SCL 6 A A A A A C1 C2 C3 C4 C5 C6 50Hz C12 C13 C18 4 GND SDA 5 T T T T T x2401 SMD + - 22p 22p 470n 100n 100V 100V 220u 100n 10u T1 T2 T3 SMD SMD SMD SMD 40V SMD 25V EEPROM S 8 4 1 M -5V D LS L D3 IC7 R11 79L05 120k 1N4001 C7 C17 C19 IC3 SMD/1% -5V C10 47u 100n 10u +5V 330p IC4 +5V 25V SMD 25V 2 - SMD 1 7 VEE C 9 4 A + IC3 % 4 7 B 10 IC3 D k 3 + 5 0 / 2 6 A 11 5 k D 8 M 8 1 6 R 3 M 5 5 R
BLANKED ? NO INTERCONNECTION D OF LX-DISPLAY . Y E S OUTPUTSIGNALOF D2901,02902, ” 1 2 9 0 3 O F B LS E G M E N T S : B A C K P LS I G N ? LT H E NO CHECK D2901, ne OUTPUTaneL “ L D L seoment 12902,02903 OUTPUT T L L SEGMENT ; ~~ R E F T O TABLE F O R C O N N E C T I O N S Y E S CHECK NOTE:MEASURING
data output during program verification. Port 0 can sink (and in bus operations can source) eight LS TTL loads. P o r1t Port 1 is an 8-bit quasi-bidirectional I/O port. It is also used for the low-order address byte during program verification. Port 1 can sink/source four LS TTL loads. P o r2t Port
lrlotorbaustein Rücklauf muß zuischen Getriebehebel I und An- schlagtappen der Brücke I ein SpieIVon 0,05 - Der lvlotormuß ohne Verkanten ins Gehäuse eingetegt 0,1 mm vorhanden sein. uerden und darfl bei einer seit-Iichen Belastung EinsLetluna: Durch Biegen des Justagelupp"n"f von 0,60 N (1 N = 102 p) an
the Source and Gate Pins to Internal Device Center of Die Inductances D Internal Source Inductance LS Measured from the Source - 12.5 - nH Lead, 6.0mm (0.25in) from LD Header to Source Bonding Pad G L S S Thermal Resistance, Junction to Case R - - 0.70 oC/W θJC Thermal Resistance, Junction to Ambient
of representation units £2200 Acuracy ++(0.5%ofreading+0.1%offulscale) Temperature coefficient +0.05%/°C Voltagedropatendofrange :200 m A range<60mV < 3 0 0 m v at 1 0 A in 20 A range < 2 0 0 m V 1 4 Response time < 1 sincluding, < 0.5sexcluding ranging Protected up to +250 mVems range 20 mA, 200 mA
dt = 200A/µs ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRLB8748PbF 1000 1000 VGS VGS TOP 10V TOP 10V 9.0V 9.0V A 5.5V A 5.5V t 4.5V t 4.5V e 4.0V e 4.0V u 100 3.5V u100 3.5V C BOTTOM 3.0V C BOTTOM 3.0V e e u u o o 3.0V - - - - i 10 3.0V
IC Revision history of SSD1315 Specification Version Change Items Effective Date st 1.0 1 Release 05-Jan-17 1.1 Revise typo of number of ISEG in DC characteristics 02-May-17 Solomon Systech Apr 2017 P 2/36 Rev 1.1 SSD1315 CONTENTS 1 GENERAL DESCRIPTION ...............................................
IC Revision history of SSD1315 Specification Version Change Items Effective Date st 1.0 1 Release 05-Jan-17 1.1 Revise typo of number of ISEG in DC characteristics 02-May-17 Solomon Systech Apr 2017 P 2/36 Rev 1.1 SSD1315 CONTENTS 1 GENERAL DESCRIPTION ...............................................
0,27 bis/to 0,35 0,95 0,10 0,92 0,10idal tape core with synthet0,92oat. Layer thickness approx. 0,05 mm to 2 mm. = S The coat is applied with whirl-sintering method. This method allows the winding of 0,05 0,88 0,05 0,88 the toroidal tape core without additional insulation. Füllfaktor η fill Factor η
* Dimension drawings in mm b 16.0 max. mm th 6.0 max. mm h 23.0 max. mm LL 25.0 min.) mm LD 1.0 ±0.05 mm LS 7.5 ±0.08 mm 1) Seating plane to IEC 60717 2) Effective Lead length acc. taping spec. IEC 60286-2 Approx. weight: 3 g PPD VAR PD 2021-04-22 Please read Cautions and warnings and Page 3 of 15 Important
n, daß, we nn diese ttenuaft® Filte05 Anzeigerr nicht Ieuchten, die andere ] A swahlmoglichkeit (lMΩ(IMQ, AC X1 l o er k in Filter) aktiv ist. Ein leuchtender R emote-Anzeigerr bedeutet, daß dasG erät n der B etriebsart Remote ist. Anmerkung
Schaltungen, d.h. die bei- den Peripheriebausteine 8155 (IS 1und IS 2) sowie das Doppel-D-Latch 54LS74 (IS 9) werden mit Hilfe des Chip-Select-Decoders 54LS139 (IS 7) angesprochen. Der Decoder selbst tritt durch die Adresse AXXXH in Funktion, das bedeutet HLHL fur die vier hochst- wertigen Adressenbits
57.8dBu) to10mV (–37.8dBu) ±1.0 dB Input >10 mV (–37.8 dBu) to 1.946 V (+8 dBu) ±0.1 dB, typically ±0.05 dB, 50 Hz to 10 kHz Input >1.946 V (+8 dBu) to <64 V (+36 dBu) for ±0.15 dB, typically ±0.05 dB, 50 Hz to10 kHz input frequency below 20 kHz and to <16 V (+26 dBu) for input frequencies from 20 to 80
capacitor is represented in figure below. Figure 10. Equivalent high-frequency circuit of a capacitor C 0 LS R S The resistor RSis the equivalent series resistance (ESR) and represents all ohmic losses of the capacitor. The inductor LSis the equivalent series inductance (ESL) and its value is function of the
needs to be set or reading the data bits on PWM. For security reasons, it cleared depending on the LS bit of the memory map is not possible to execute a Verify function without first (Key 0) before the key is clocked in to the HCS361. S1 programming the EEPROM. A Verify operation can must remain at this
dem Datum Das Fazitdieses Forums istder Wunsch läßtsich das anhand von einigenBeispie 29.10. um 0.05 Uhr ausgedruckt istViele an die Rundfunkanstalten, insbesondere len erklären. Recorderbesitzer haben ihreGeräte ent die ARD, den VPS-Dienst präziser abzu Laut Programmplanung einer Sendean sprechend
one bit to the right (toward the LSB), zero–filling the MSB. Extract and examine the L.B 4. (If the LS was 0): Repeat S tep 3 (another shift). (If the LSB was 1): Exclusive OR the CRC register with the polynomial value 0xA001 (1010 0000 0000 0001). 5. R epeat Steps 3 and 4 until 8 shifts have been performed
be polled until bit[0] is set before this register may be read. This register is readonly. Status 0x05 Bit[0] when set indicates it is okay to read the next data byte from the Resource Data register. This register is readonly. Card Select Number 0x06 A write to this port sets a card’s CSN. The CSN is
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