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Datei
counter.vhd
unsigned(N-1 downto 0); begin -- register process(clk,reset) begin if (reset='1') then r_reg <= (others=>'0'); elsif (clk'event and clk='1') then r_reg <= r_next; end if; end process; -- next-state logic -- r_next <= (others=>'0') when -- r_reg=(N-1) -- else -- r_reg + 1; r_next <= r_reg + 1; -- output logic q <= std_logic_vector(r_reg); max_tick <= '1' when r_reg=(M-1) else '0'; end arch;
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Datei
SineLUT.vhd
"; when "000000100" => sin_out_tmp <= "10000110011011"; when "000000101" => sin_out_tmp <= "10001000000010"; when "000000110" => sin_out_tmp <= "10001001101001"; when "000000111" => sin_out_tmp <= "10001011001111
in „EduBoard DE2-115 & DAC - erzeugtes Signal weicht erheblich von dem erwarteten ab“ · FPGA, VHDL & Co. ·
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Datei
SquareLUT.vhd
<= "11111111111111"; when "000000100" => square_out_tmp <= "11111111111111"; when "000000101" => square_out_tmp <= "11111111111111"; when "000000110" => square_out_tmp <= "11111111111111"; when "000000111" => square_out_tmp
in „EduBoard DE2-115 & DAC - erzeugtes Signal weicht erheblich von dem erwarteten ab“ · FPGA, VHDL & Co. ·
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PDF
RGS24128064YW001.pdf
shall be disclosed to others or duplicated or used for others without the express written consent of RiTdisplay. http://www.ritdisplay.com 6. ELECTRICAL CHARACTERISTICS 6.1 D.C ELECTRICAL CHARACTERISTICS SYMBOL PARAMETERS TEST
in „Wer hat Infos zum OLED Display RGS24128064YW (Ritek)“ · Mikrocontroller und Digitale Elektronik ·
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Datei
LogicA.vhd
0), y => Y(3 downto 0), c => conv_std_logic_vector(character'pos(txt),8), p => p ); red <= "1111" when (BLANK='1' and ((Y=300 and sig(conv_integer(X))='1') or (Y=350 and sig(conv_integer(X))='0'))) else charcolor(8 to 11) when BLANK='1' and p='1' else "0000"; green <= charcolor(4 to 7) when BLANK='1' and p='1' else "0000"; blue <= charcolor(0 to 3) when BLANK='1' and p='1' else "0000"; end architecture;
in „[LIN-Bus] Slave reagiert nicht“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Morse_Trainer.vhd
C when 3 => Buchstabe <= "0000110101"; -- D when 4 => Buchstabe <= "0000000001"; -- E when 5 => Buchstabe <= "0001011101"; -- F when 6 => Buchstabe <= "0000111101"; -- G when 7 => Buchstabe <= "0001010101"
in „Altera DE2-115 mit Cyclone IV - Hardware verhält sich anders als die Simulation (ModelSim)“ · FPGA, VHDL & Co. ·
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PDF
MC14538B.PDF
capacitor X completely charged inhibited andtheQandQ outputs of the output latch will not to VDD . When the trigger input A goes from V SS to V DD change. Since the Q output is reset when an input low level (while inputs B and Reset are held to V ) a valid trigger is DD is detected on the Reset input,
in „Platine Bedieneinheit mit Oszi durchmessen“ · Platinen ·
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PDF
SAMSUNG-INR21700-40T-Datasheet.pdf
above and excludes in the case of a defect which is not related to manufacturing of the cell. 11.0. Others 11.1 Storage for a long time If the cell is kept for a long time (3 months or more), It is strongly recommended that the cell is preserved at dry and low-temperature. 11.2 Others Any matters that specifications
in „Einweg-Vape erforschen :-)“ · Analoge Elektronik und Schaltungstechnik ·
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Datei
dreh_top.vhd
= '0'; error <= '1'; when "0100" => up_down <= '0'; ce <= '1'; error <= '0'; when "0101" => up_down <= '0'; ce <= '0'; error <= '0'; when "0110" => up_down <= '1'; ce <= '0'; error <= '1'; when "0111" => up_down <= '1'; ce <
in „Signalteiler“ · FPGA, VHDL & Co. ·
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Datei
clock_gen_v1.vhd
| 5µs when "0100" => cnt_div <= 20-1; -- 4 | 2.500Mhz | 10µs when "0101" => cnt_div <= 40-1; -- 5 | 1.250Mhz | 20µs when "0110" => cnt_div <= 100-1; -- 6 | 500.000khz | 50µs when "0111" => cnt_div <= 200-1; --
in „[VHDL] Daten von ADC in BRAM speichern“ · FPGA, VHDL & Co. ·
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Datei
bin2bcd.vhd
: std_logic_vector(0 to digits-1); begin with rst select shift_i <= data & shift_o(0 to digits-2) when '1', (0 => data, others => '0') when others; shifters : for i in 0 to digits - 1 generate shifter : bcdshifter port map ( clk => clk, rst => rst, s_in => shift_i(i), s_out => shift_o(i), bcd => result
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Datei
ASCIIPckg.vhd
WHEN f =>VectorOut:="0111000";--geändert WHEN g =>VectorOut:="0000001"; WHEN h =>VectorOut:="1101000"; WHEN i =>VectorOut:="1111001"; WHEN j =>VectorOut:="1000011"; WHEN k =>VectorOut:="1110000"; WHEN l
in „RS232 Daten Empfangen, Vergleichen, auf Monitor ausgeben (SPARTAN 3)“ · FPGA, VHDL & Co. ·
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Datei
PWM.vhd
when "1101" => pwmvalue <= "1000"; -- Position 4 8 when "0101" => pwmvalue <= "1010"; -- Position 5 10 when "1001" => pwmvalue <= "1011"; -- Position 6 11 when "0001" => pwmvalue <= "1100"; -- Position 7 12 when "1110" => pwmvalue <= "1101"; -- Position 8 13 when "0110" => pwmvalue <= "1110"; -- Position 9 14 when others => pwmvalue <= "0000"; end case; wait until rising_edge(clkin); counter <= counter + "0001
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Datei
Enigma.vhd
port ( clock : in std_logic; data_in : in std_logic_vector(0 to data_width - 1); -- loaded is high when the rotor has been loaded with all characters loaded : out std_logic; -- hit is high when a character is found on the rotor otherwise low hit : out std_logic; read_address : in std_logic_vector(0 to address_width - 1); write_enable : in std_logic; read_enable : in std_logic; -- Set lookup high when you are searching for a character lookup : in std_logic; data_out : out std_logic_vector(0 to data_width - 1) := (others => '0'); -- Set rotate high when you want to rotate (position <= position + 1
in „Problem mit der Zuweisung von Prameters bei generate“ · FPGA, VHDL & Co. ·
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Datei
Test.txt
when "00001001" => M1 <= "00010010"; --September 09->18 when "00001010" => M1 <= "00010100"; --Oktober 10->20 when "00001011" => M1 <= "00010111"; --November 11->23 when "00001100" => M1 <= "00011001"; --Dezember 12->25 when others => M1 <= "00000000"; end case; end process; M2 <= To_StdLogicVector(M1); D1 <= To_StdLogicVector(D); C1 <= To_StdLogicVector(C); Y1 <= To_StdLogicVector(Y); --Allgemeine Wochentagsformel nach
in „Fehlermeldung“ · FPGA, VHDL & Co. ·
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Datei
zaehler.vhd
downto 0)); -- 7-Segm. - Ausgangsvektor end DEK7; ARCHITECTURE v1 OF dek7 IS BEGIN b <= "1000000" WHEN a = "0000" ELSE -- H"40" "1111001" WHEN a = "0001" ELSE -- H"79" "0100100" WHEN a = "0010" ELSE -- H"24" "0110000" WHEN a = "0011" ELSE -- H"30" "0011001" WHEN a = "0100" ELSE -- H"19" "0010010" WHEN a = "0101" ELSE -- H"12" "0000010" WHEN a = "0110" ELSE -- H"02" "1111000" WHEN a = "0111" ELSE -- H"78" "0000000" WHEN a = "1000" ELSE -- H"00" "0010000" WHEN a = "1001" ELSE -- H"10" "0001000" WHEN a = "1010" ELSE -- H"08" "0000011" WHEN
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Datei
TristateImFPGA.vhd
Komponente port map (sel=>sel, data=>daint, dout=>doint); daint <= da; dbint <= db; doint <= dbint when (ena='1') else (others=>'Z'); do <= doint; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity Komponente is Port ( sel : in STD_LOGIC; dout : out STD_LOGIC_VECTOR
in „AX8 - PINB - Multi-source-Error (Spartan 3E/VHDL)“ · FPGA, VHDL & Co. ·
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PDF
ST29F400BB.pdf
references tween the 8-bit and 16-bit Bus modes of the mem- to the Data Input/Output to include this pin when ory. When Byte/Word Organization Select is Low, BYTE is High and references to the Address In- VIL, the memory is in 8-bit mode, when it is High, puts to include this pin when BYTE is Low except VIH
in „AT91 & OpenOCD Externes Flash Problem“ · Mikrocontroller und Digitale Elektronik ·
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PDF
6581.pdf
references tween the 8-bit and 16-bit Bus modes of the mem- to the Data Input/Output to include this pin when ory. When Byte/Word Organization Select is Low, BYTE is High and references to the Address In- VIL, the memory is in 8-bit mode, when it is High, puts to include this pin when BYTE is Low except VIH
in „Externes Flash M29F400B ansprechen“ · Mikrocontroller und Digitale Elektronik ·
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Datei
counter.vhd
Counter: process(ClkLeft,ModeLeft) is begin if ClkLeft'event AND ModeLeft ='1' then case LED_out is when "00000001" =>LED_out <="00000010"; when "00000010" =>LED_out <="00000100"; when "00000100" =>LED_out <="00001000"; when "00001000" =>LED_out <="00010000"; when "00010000" =>LED_out <="00100000"; when "00100000" =>LED_out <="01000000"; when "01000000" =>LED_out <="10000000"; when "10000000" =>LED_out <="00000001"; when others => null; end case; else null; end if; end process Counter; LED<=LED_out; end architecture behaviour;
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Datei
Frequency_Generator.vhd
; when "00100" =>frequency_out <= frequency_divider(3); when "00101" =>frequency_out <= frequency_divider(4); when "00110" =>frequency_out <= frequency_divider(5); when "00111" =>frequency_out <= frequency_divider
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Datei
FIRFilter_LeftChannel.vhd
- 1) of std_logic_vector(3 * DSIZE - 1 downto 0); -- 48 Bit Akkumulator signal a_sop : ASOP := ( others => x"000000000000" ); --type ACOEF is array (0 to NBTAP - 1) of std_logic_vector(0 to DSIZE - 1); --signal a_coeff : ACOEF := ( others => x"0000" ); type ACOEF is array (0 to NBTAP - 1) of std_logic_vector
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
FIRFilter_RightChannel.vhd
- 1) of std_logic_vector(3 * DSIZE - 1 downto 0); -- 48 Bit Akkumulator signal a_sop : ASOP := ( others => x"000000000000" ); --type ACOEF is array (0 to NBTAP - 1) of std_logic_vector(0 to DSIZE - 1); --signal a_coeff : ACOEF := ( others => x"0000" ); type ACOEF is array (0 to NBTAP - 1) of std_logic_vector
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
BarrelShifter.vhd
ShiftData : std_logic_vector (BarrelWidth-1 downto 0); signal slot : unsigned(slotbits-1 downto 0) := (others => '0'); -- Welcher Slot muss als nächstes geladen werden? signal cnt : unsigned(log2(BarrelWidth)-1 downto 0) := (others => '0'); -- Aktuelle Fensterposition signal nbits : integer range 0 to BarrelWidth
in „Prozess mit kombinatorischer und getakteter Logik“ · FPGA, VHDL & Co. ·
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Datei
vga.vhd
STD_LOGIC; SIGNAL sl_vsync : STD_LOGIC; SIGNAL usig_hcount : unsigned (c_htotal_bits-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL usig_vcount : unsigned (c_vtotal_bits-1 DOWNTO 0) := (OTHERS=>'0'); begin clock_divide : PROCESS --640x480 hat ca 25 MHz pixel clk BEGIN WAIT UNTIL rising_edge( isl_clk50 ); sl_clken
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PDF
doc8002.pdf
purpose of this register is to be able to tune the oscillator frequency. This tuning is utilized when calibrating the RC oscillator. When calibrating using an external crystal, the device timer must have the possibility to operate asynchronously of the system clock. When a device is calibrated by Atmel
in „Genauigkeit interner Oszillator Mega8 ...“ · Mikrocontroller und Digitale Elektronik ·
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Datei
melodyGenerator.vhd
state = 5 else '1'; leds(6) <= '0' when state = 6 else '1'; leds(7) <= '0' when state = 7 else '1'; -- note player sequencer with state select prescaler <= NOTE_C4 when 0 , NOTE_D4 when 1 , NOTE_E4 when 2 , NOTE_F4 when 3 , NOTE_G4 when 4 , NOTE_A4 when 5 , NOTE_H4 when 6 , NOTE_C5 when others ; end Behavioral;
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Datei
melodyGenerator.vhd
state = 5 else '1'; leds(6) <= '0' when state = 6 else '1'; leds(7) <= '0' when state = 7 else '1'; -- note player sequencer with state select prescaler <= NOTE_C4 when 0 , NOTE_D4 when 1 , NOTE_E4 when 2 , NOTE_F4 when 3 , NOTE_G4 when 4 , NOTE_A4 when 5 , NOTE_H4 when 6 , NOTE_C5 when others ; end Behavioral;
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Datei
4bit_alu.vhd
Eingangsoperand SIGNAL B: STD_LOGIC_VECTOR(3 DOWNTO 0); begin alu: PROCESS(F,A,B) BEGIN CASE F IS WHEN "0100"=> S <= A + B;--Addition A,B WHEN "0101"=> S <= A - B;--Subtraktion A,B WHEN "0110"=> S <= A + 1;--Increment A WHEN "0111"=> S <= A - 1;--Decremen A WHEN "1000"=> S <= NOT A;--Negation A WHEN
in „4-bit_ALU“ · FPGA, VHDL & Co. ·
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PDF
Cosel_LEB100F-512.pdf
CISPR22-B EN55022-B VCCI-B REGULATIONS HARMONIC ATTENUATOR Complies with IEC61000-3-2 *9 ( ) ( ) OTHERS CASE SIZE/WEIGHT 75X35 X22mm [2.95 1.X8 8.7X inches] W H D X X0g max with chassis & cover : 690g max COOLING METHOD Convection *1 Specification is changed at option, refer to Instruction Manual 5.
in „Schaltnetzteil Cosel LEB100F-512 Fehlersuche“ · Analoge Elektronik und Schaltungstechnik ·
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Datei
sd-wandler.txt
signed; signal dIn_un: unsigned (9 downto 0); begin -- Signale mit '0' initalisieren -- doutm <= (others => '0'); din_alt <= (others => '0'); Differenz: process (dIn, dOutm) -- Differenzbildung am 1. Knoten -- begin dIn_temp <= dIn - dOutm & '0'; end process Differenz; Addiere: process (dIn_temp, dIn_alt
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Datei
A90S8535.vhd
Port_OutC when "010101", -- $15 DirC when "010100", -- $14 Port_InC when "010011", -- $13 Port_OutD when "010010", -- $12 DirD when "010001", -- $11 Port_InD when "010000", -- $10 UDR when "001100", -- $0C USR & "000" when "001011", -- $0B UCR(7 downto 1) & "0" when "001010", -- $0A UBRR when "001001", -- $09 "--------" when others; end generate; gTri : if TriState generate IO_RData <= SREG when IO_Addr = "11" & x"F"
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PDF
AVR506.pdf
Application Note • IO pinsources 1 Introduction This application note summarizes the relevant differences when migrating from ATmega169 to ATmega169P. For detailed information on the devices please see the respective datasheets. The ATmega169P is designed to be pin and functionality compatible with ATmega169
in „Bascom atmega169P“ · Mikrocontroller und Digitale Elektronik ·
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Datei
bitcount.vhd
(inp : std_logic_vector(3 downto 0)) return integer is variable res : integer; begin case inp is when "0000" => res := 0; when "0001" => res := 1; when "0010" => res := 1; when "0011" => res := 2; when "0100" => res := 1; when "0101" => res := 2; when "0110" => res := 2; when "0111" => res := 3; when "1000" => res := 1; when "1001" => res := 2; when "1010" => res := 2; when "1011" => res := 3; when "1100" => res := 2; when "1101" => res := 3; when "1110" => res := 3; when "1111" => res := 4; when others => res := 0; --
in „Weils so schön war : Einsen Zählen II“ · FPGA, VHDL & Co. ·
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Datei
ADWLTC1286.vhd
when 8 => TMP(8) := Data; ct:= ct+1; when 9 => TMP(7) := Data; ct:= ct+1; when 10 => TMP(6) := Data; ct:= ct+1; when 11 => TMP(5) := Data; ct:= ct+1; when 12 => TMP(4) := Data; ct:= ct+1; when 13 => TMP(3) := Data; ct:= ct+1; when 14 => TMP(2) := Data; ct:= ct+1; when 15 => TMP(1) := Data; ct:= ct+1; when 16 => TMP(0) := Data; ct:= ct+1; when 17 => CS <= HIGH; ct:= ct+1; DataLTC <= TMP; --DataLTC <= ("111010000000"); when others
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Datei
bcd_to_7seg.vhd
; c <= '1'; d <= '0'; e <= '0'; f <= '1'; g <= '0'; when "0011" => a <= '0'; b <= '0'; c <= '0'; d <= '0'; e <= '1'; f <= '1'; g <= '0'; when "0100" => a <= '1'; b <= '0'; c <= '0'; d <= '1'; e <= '1'; f <= '0'; g <= '0'; when "0101" => a <= '0'; b <= '1'
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PDF
DEM240128D_SBH-PW-N.pdf
Supply(+5V) 7 V0 Power Supply for LCD Drive(-15V) 9 /WR Data write. Write data to controller T6963C when “L” 11 /RD Data read. Read data from controller T6963C when “L” 13 /CE Chip enable of controller when “L” Command/Data read/write. “H” for command read/write and 15 C/ D “L” for data read/write 17 /
in „Display mit T963C“ · Mikrocontroller und Digitale Elektronik ·
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PDF
RIT_Display_rgs24128064yw002-09703_TAB_-A01__2_.pdf
contains confidential and propNeither it nor the information contained herein shall be disclosed to others or duplicated or used for others without the express written consent of RiTdisplay. http://www.ritdisplay.com REVISION RECORD REV. REVISION DESCRIPTION REV. DATE REMARK X01 INITIAL RELEASE 2005. 08
in „RitDisplay???“ · Mikrocontroller und Digitale Elektronik ·
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PDF
MCU_-_HR8P506_Datasheet_e.pdf
PB10 and PB11(default) Internal HRC clock frequency select bit INTOSC_SEL bit6 0:16MHz (default) 1: Others (for internal test only, prohibited to set to 1) 140ms power-on time enable bit 0:Enabled (default) CFG_PWRTEB bit7 1:Disabled This bit is valid only when the MRSTN pin is used for external reset (
in „Re - Programmierung eines Cortex M0“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Inzialisator.vhd
FULL_COUNT; -- begin if Reset = '1' then Index_a := 0; elsif (Clk'event AND Clk='1') then CASE Go is when '0' => if (Ready = '1') then Go <= '1'; end if; when '1' => SLWR <= '0'; -- DATA <= DataTab_a; Go <= '2'; when '2' => SLWR <= '1'; Go <= '3'; when '3' => Go <='0'; Index_a := Index_a + 1; end case;
in „Fehler ohne Fehler ausgabe bei alzium“ · FPGA, VHDL & Co. ·
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Datei
code.txt
Wandlung when 2 => Zustand <= "0010"; convst <= '0'; rd <= '1'; cs <= '1'; timeout <= 30; --Zählvariable fals bei Einschaltvorgang in when3 oder 4 gesprungen wird switch <= '0'; state_ADC <= 3; --Warten auf busyadc
in „state machine“ · FPGA, VHDL & Co. ·
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Datei
Main.vhd
cntkHz - 1; end if; end if; end process; -- Anoden select with index select anodBits <= "000001" when 0, "000010" when 1, "000100" when 2, "001000" when 3, "010000" when 4, "100000" when 5; -- Wert nach 7 Segment codieren with (digits(index)) select -- abcdefg ssegBits <= "1111110" when x"0", "0110000" when x"1", "1101101" when x"2", "1111001" when x"3", "0110011" when x"4", "1011011" when x"5", "1011111" when x"6", "1110000" when x"7", "1111111" when x"8", "1111011" when x"9", "0000000" when others; ANOD
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Datei
divider.vhd
to 1999 := 0; signal clock_dvd : std_logic := '0'; begin process (divider) begin case divider is when "0000" => count_to <= 1-1; --div by 2 ->50ns when "0001" => count_to <= 2-1; --div by 4 -> 100ns when "0010" => count_to <= 4-1; --div by 8 -> 200ns when "0011" => count_to <= 10-1; --div by 20 -> 500ns when "0100" => count_to <= 20-1; --div by 40 -> 1µs when "0101" => count_to <= 40-1; --div by 80 -> 2µs when "0111" => count_to <= 100-1; --div by 200 -> 5µs when others => count_to <= 1-1; end case; end
in „Allererster Versuch - Frequenzteiler“ · FPGA, VHDL & Co. ·
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PDF
1-Walther__Article.pdf
shoot or shock others. I also have no control over others and how they might use this information. For these reasons the following warnings must be presented: Warning: The reader must assume full responsibility for any
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PDF
VHDL-Cookbook.pdf
red => statements for red; when green | blue => statements for green or blue; when orange to turquoise => statements for these colours; end case; case opcode of when X"00" => perform_add; when X"01" => perform_subtract; when others
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Datei
7segment.vhd
rising_edge(clk); case data_int is -- da ich ohnehin noch keine hardware habe, scheint mir das ausreichend when "0000" => segments <= "0000000"; when "0001" => segments <= "0000001"; when "0010" => segments <= "0000011"; when "0011" => segments <= "0000111"; when "0100" => segments <= "0001111"; when "0101" => segments <= "0011111"; when "0110" => segments <= "0111111"; when "0111" => segments <= "1111111"; when others => segments <= "0000000"; end case; if (oe = '1') then enable <= '1'; else enable <= '0'; end if; end process; data_int
in „Der vhdl-Schnipsel-Anfängerfragen Thread“ · FPGA, VHDL & Co. ·
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Datei
Kaffeeautomat_FSM0b.vhd
Z : zustaende := warte ; begin -- Einsynchronisieren Pr50Csr <= Pr50Csr(3 downto 0)&Pruefer50Cent when rising_edge(clk); Pr1Esr <= Pr1Esr(3 downto 0) &Pruefer1Euro when rising_edge(clk); Pr2Esr <= Pr2Esr(3 downto 0) &Pruefer2Euro when rising_edge(clk); -- Flankenerkennung Pr50C <= '1' when Pr50Csr(4
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Datei
FIRFilter.vhd
- 1) of std_logic_vector(3 * DSIZE - 1 downto 0); -- 48 Bit Akkumulator signal a_sop : ASOP := ( others => x"000000000000" ); type ACOEF is array (0 to NBTAP - 1) of std_logic_vector(0 to DSIZE - 1); signal a_coeff : ACOEF := ( others => x"0000" ); begin blk_mem_gen : blk_mem_gen_0 PORT MAP ( clka =>
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
VHDL-Code.txt
std_logic_vector(buswidth-1 downto 0) := x"00"; begin SIWU <= '1'; --If not used tie this pin to Vcc tx <= '1' when TXE = '0' and ft2232_wait = 1 and rdempty = '0' else '0'; rx <= '1' when RXF = '0' else '0'; state_tx<= '1' when tx_ = '1' else '0'; state_rx <= '1' when bus_oe_mode > 1 and rx = '1' and tx = '0' else '0'; rdreq <= '1' when state_tx = '1' else '0'; WR <= '0' when state_tx = '1' else '1'; RD <= '0' when state_rx = '1' else '1'; OE <= '0' when bus_oe_mode > 0 else '1'; usb_data <= data_tx when state_tx = '1' else (others
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PDF
wg160128b_datasheet.pdf
LCD contrast adjustment 5 Vee Negative voltage Output 6 /WR L Data write. Write data into T6963C when /WR = L 7 /RD L Data read. Read data from T6963C when RD = L 8 /CE L Chip enable the controller T6963C 9 C/D H / L WR=L , C/D=H : Command Write C/D=L: Data write RD=L, C/D=H : Status Read C/D=L: Data
in „GLCD Kontrast (WG160128B & T6963c)“ · Mikrocontroller und Digitale Elektronik ·