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PDF
SC17_GENERAL_MAG_98_1.pdf
can be determined and simply compensated for by applying the appropriate current to the coils, synthesizing a compensation field. Continuous alignment With high-end compass applications, the microcontroller can also be used to adjust the calibration of the compass continually. This is especially useful
in „Typical Application Circuit - Kondensatoren wechselbar?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SC17_GENERAL_MAG_98_1.pdf
can be determined and simply compensated for by applying the appropriate current to the coils, synthesizing a compensation field. Continuous alignment With high-end compass applications, the microcontroller can also be used to adjust the calibration of the compass continually. This is especially useful
in „Suche einen Magnetfeldsensor“ · Mikrocontroller und Digitale Elektronik ·
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PDF
19230ds.pdf
DC input will degrade the accuracy to approximately 4 arc minutes. It is recommended that the synthesized reference option be dis- abled for DC input operation. Disable the synthesized reference by connecting pin 52, DSR , to ground through a 10 ohm resistor. VELOCITY TRIMMING The reference input is
in „Stimulierung des Resolvers RD-19230“ · Mikrocontroller und Digitale Elektronik ·
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PDF
IA4421-DS.pdf
of the control bit Related blocks er Enables the whole receiver chain RF front end, baseband, synthesizer, crystal oscillator ebb The receiver baseband circuit can be separately switchedBaseband et Switches on the PLL, the power amplifier, and starts thePower amplifier, synthesizer, crystal oscillator
in „Software SPI zur Chip Konfig“ · Mikrocontroller und Digitale Elektronik ·
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PDF
s1d13700.pdf
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 15-6 Layer Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 15-7 Half-Tone Character And Graphics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 15-8
in „Quarz für S1D13700“ · Mikrocontroller und Digitale Elektronik ·
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Datei
spi_master.vhd
-- -- Permission: -- -- Lattice Semiconductor grants permission to use this code for use -- in synthesis for any Lattice programmable logic product. Other -- use of this code, including the selling or duplication of any -- portion is strictly prohibited. -- -- Disclaimer: -- -- This VHDL or Verilog
in „unklares Signalverhalten eines SPI-Moduls“ · Mikrocontroller und Digitale Elektronik ·
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Datei
pwm2.vhd
*************************** -- erzeugung eines pwm-signals zur h-brückenansteuerung mit(vor der synthese) wählbarer auflösung. -- bausteine: xilinx xc9572, xc9536 -- die pwm-daten werden unabhängig vom zustand des pwm-generators seriell eingeschrieben und erst -- nach beendigung des laufenden pwm-zyklus
in „hardware-pwm mit variabler auflösung in xilinx cpld“ · Projekte & Code ·
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Datei
ether_tx.vhd
std_logic; fifo_full : buffer std_logic; fifo_empty : buffer std_logic ); end ether_tx; architecture synth of ether_tx is -------------------------------------------------------------------- function crc (data_in:std_logic_vector (7 downto 0); crc_value:std_logic_vector(31 downto 0)) return std_logic_vector
in „Ethernet GMII“ · FPGA, VHDL & Co. ·
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Datei
rfm02.inc
control Bit1 = 0 ;a0 : Automatic control Bit0 = 0 ;ex : Enable crystal oscillator = 1 ;es : Enable synthesizer = 0 ;ea : Enable power amplifier = 0 ;eb : Enable low battery detector = 1 ;et : Enable wake-up timer = 0 ;dc : Disable clock output = 0 .equ RFM_pwr_mgmt_PwrOnH = 0xC0 .equ RFM_pwr_mgmt_PwrOnL
in „[AVR-ASM] RFM02 funktioniert plötzlich nicht mehr“ · Mikrocontroller und Digitale Elektronik ·
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Datei
kompletter_log.txt
issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Process "Synthesis" failed
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Datei
can_fifo.v
01:13:38 mohor // backup. // // Revision 1.7 2003/01/17 17:44:31 mohor // Fifo corrected to be synthesizable. // // Revision 1.6 2003/01/15 13:16:47 mohor // When a frame with "remote request" is received, no data is stored // to fifo, just the frame information (identifier, ...). Data length // that
in „BlockRAM Primitive Spartan 3E gegen Spartan 6“ · FPGA, VHDL & Co. ·
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Datei
System.cpp
salve.y(system_signal4); slave_Trans.y(system_signal4); } }; #if !defined(AGILITY) && !defined(SC_SYNTHESIS) int sc_main(int argc, char* argv[]) { sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING); System top_level("top_level"); sc_start(); return 0; } #endif
in „PLB- Bus mit System C“ · Mikrocontroller und Digitale Elektronik ·
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Datei
162_ICP_DDS_01.c
Messung der Herzfrequenz über ICP, Berechnung der daraus //resultierenden Therapiefrequenz und deren Synthese mit DDS 24.1.2011 #include <inttypes.h> #include <avr/interrupt.h> #include <avr/io.h> #include <stdint.h> #include <stdlib.h> #include <string.h> #include <avr/io.h> #ifndef TRUE #define TRUE 1 #
in „Atmega162 außerhalb von STK500 geht nicht“ · Mikrocontroller und Digitale Elektronik ·
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Datei
162_ICP_DDS_02.c
Messung der Herzfrequenz über ICP, Berechnung der daraus //resultierenden Therapiefrequenz und deren Synthese mit DDS 24.1.2011 #include <inttypes.h> #include <avr/interrupt.h> #include <avr/io.h> #include <stdint.h> #include <stdlib.h> #include <string.h> #include <avr/io.h> #ifndef TRUE #define TRUE 1 #
in „DDS Signal stoppt nicht bei ICP ohne Eingang“ · Mikrocontroller und Digitale Elektronik ·
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Datei
rf12.h
Base Band Block, Enable Transmitter, Enable Synthesizer, Enable Crystal Oscillator, !Enable Low Battery Detector, !Enable Wake-Up Timer, Disable Clock Output of CLK-Pin #define RF12_TX_off RF12_cmd (RF12_CMD_PWR | 0b00000001); // !Enable Receiver, !Enable
in „RFM 12 Probleme“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Spezifikation.pdf
Semiconductors 2 The I C-bus specification handbook, full pagewidth SDA SCL MICRO- CONTROLLER PCB83C528 PLL SYNTHESIZER TSA5512 NON-VOLATILE MEMORY PCF8582E M/S COLOUR DECODER TDA9160A STEREO / DUAL SOUND DECODER TDA9840 SDA SCL PICTURE DTMF SIGNAL GENERATOR IMPROVEMENT TDA4670 PCD3311 HI-FI LINE AUDIO INTERFACE
in „SPI, ISP, USI, TWI, I2C“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Java_3.Auflage.pdf
wiedergegeben, sondern auch aufgenommen und bearbeitet werden, und es ist möglich, Zusatzgeräte wie Mixer, Synthesizer oder andere Audiogeräte anzusteuern. Die Ausgabe von Sound ist denkbar einfach und kann auf zwei unterschiedliche Arten erfolgen. Zum einen stellt die Klasse Applet die Methode play( ) zur Verfügung
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PDF
xapp105_CPLD_VHDL_Introduction.pdf
to structure circuits in many levels of detail. This versatility also makes the job of the VHDL synthesis tool a lot more complex, and there is latitude for interpretation depending on the VHDL coding style. One synthesis tool may implement the same code very differently from another. In order to achieve
in „xilinx CPLD“ · FPGA, VHDL & Co. ·
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PDF
ALSE_UART_us.pdf
demonstrate, on a “real-life” example, how a sound HDL methodology can be used in conjunction with modern synthesis and simulation tools. Note : the source code we provide here if for teaching purpose only. This code belongs to ALSE. If you want to use it in your projects please contact us. © Bertrand CUZEAU -
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PDF
HCL-ATA_host_controller.pdf
Template file India Ph : +91-44-23728366 Tools Used Fax : +91-44-24806640 Simulation Modelsim 5.8 Synthesis Synplifypro 7.3 PAR ISE6.2i Features Support • Implements ANSI ATA/ATAPI-6 standard Support through email by HCL Technolgies protocol • Supports connection up to 2 ATA devices • Configurable ATA
in „Belohnung: Wer macht mit bei meinem Projekt?“ · FPGA, VHDL & Co. ·
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PDF
KCPSM3_Manual.pdf
show suitable circuits for output ports, input ports and connection of memory. If you are using a synthesis tool, it is advisable to check that your code is not describing a circuit which is more complex than is really required and that the synthesis tool is implementing the correct logic. Simple Outputs
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PDF
sed1335.pdf
flashing 0 1 BL Error BL Error 0 0 Ruled line RL LINE RL LINE 0 1 LINE LINE 1 1 Figure 64. Layer synthesis A number of means can be used to achieve these effects, 16.5.2. Half-tone display depending on the display configuration. These are listed The FP parameter can be used to generate half-intensity
in „Extrem schwere Frage“ · Mikrocontroller und Digitale Elektronik ·
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PDF
doc4779atr2406.pdf
demodulator, RSSI, TX preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated VCO and TX filter. No mechanical adjustment is necessary in production. The RF-transceiver offers a clock recovery function on-chip. Rev. 4779G–ISM–05/05 Figure 1-1. Block
in „Gauss Anpassung Register“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ICL7660.pdf
Circuit model. Switching the bucket capacitor, C1, between the input and output of the circuit synthesizes a resis- tance (Figures 3a and 3b.) _______________Detailed Description The MAX1044/ICL7660 are charge-pump voltage con- When the switch in Figure 3a is in the left position, verters. They work
in „neg. Spannung mit Z-Diode erzeugen“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
Spezifikation.pdf
Semiconductors 2 The I C-bus specification handbook, full pagewidth SDA SCL MICRO- CONTROLLER PCB83C528 PLL SYNTHESIZER TSA5512 NON-VOLATILE MEMORY PCF8582E M/S COLOUR DECODER TDA9160A STEREO / DUAL SOUND DECODER TDA9840 SDA SCL PICTURE DTMF SIGNAL GENERATOR IMPROVEMENT TDA4670 PCD3311 HI-FI LINE AUDIO INTERFACE
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PDF
Spezifikation.pdf
Semiconductors 2 The I C-bus specification handbook, full pagewidth SDA SCL MICRO- CONTROLLER PCB83C528 PLL SYNTHESIZER TSA5512 NON-VOLATILE MEMORY PCF8582E M/S COLOUR DECODER TDA9160A STEREO / DUAL SOUND DECODER TDA9840 SDA SCL PICTURE DTMF SIGNAL GENERATOR IMPROVEMENT TDA4670 PCD3311 HI-FI LINE AUDIO INTERFACE
in „I²c mit Bascom und ATmega“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Spezifikation.pdf
Semiconductors 2 The I C-bus specification handbook, full pagewidth SDA SCL MICRO- CONTROLLER PCB83C528 PLL SYNTHESIZER TSA5512 NON-VOLATILE MEMORY PCF8582E M/S COLOUR DECODER TDA9160A STEREO / DUAL SOUND DECODER TDA9840 SDA SCL PICTURE DTMF SIGNAL GENERATOR IMPROVEMENT TDA4670 PCD3311 HI-FI LINE AUDIO INTERFACE
in „Reset auf I2C-Bus“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Philips_Semiconductors_-_I2C_Bus_Specification_v2.1.pdf
Semiconductors 2 The I C-bus specification handbook, full pagewidth SDA SCL MICRO- CONTROLLER PCB83C528 PLL SYNTHESIZER TSA5512 NON-VOLATILE MEMORY PCF8582E M/S COLOUR DECODER TDA9160A STEREO / DUAL SOUND DECODER TDA9840 SDA SCL PICTURE DTMF SIGNAL GENERATOR IMPROVEMENT TDA4670 PCD3311 HI-FI LINE AUDIO INTERFACE
in „GND-Fäche sinnvoll???“ · Platinen ·
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PDF
sn75lvds82.pdf
contains four CLKOUT 26 31 V CC serial-in 7-bit parallel-out shift registers, a 7× clock D0 27 30 D2 synthesizer, and five low-voltage differential signaling GND 28 29 D1 (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such
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PDF
fft.pdf
Aufgabenstellung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.1 Beispiel 1: Synthese . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.2 Beispiel 2: Analyse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Quellen und Anhang 24
in „KleineFrage über Mathematik“ · Digitale Signalverarbeitung / DSP / Machine Learning ·
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PDF
ds1879a.pdf
synthesizer. In Native mode, the FM synthesizer has 7 6 5 4 3 2 1 0 increased capabilities and performance for more realistic music. The following register descriptions are for This register is used to read
in „Informationen über ISA-Karten“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Spezifikation.pdf
Semiconductors 2 The I C-bus specification handbook, full pagewidth SDA SCL MICRO- CONTROLLER PCB83C528 PLL SYNTHESIZER TSA5512 NON-VOLATILE MEMORY PCF8582E M/S COLOUR DECODER TDA9160A STEREO / DUAL SOUND DECODER TDA9840 SDA SCL PICTURE DTMF SIGNAL GENERATOR IMPROVEMENT TDA4670 PCD3311 HI-FI LINE AUDIO INTERFACE
in „i2c und Takt“ · Mikrocontroller und Digitale Elektronik ·
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PDF
NE_SA612.pdf
oscillator suitable for resistor. This permits direct output termination yet allows for synthesizer-controlled applications. It is important to buffer the balanced output as well. Figure 6 shows three single-ended output output of this circuit to assure that switching spikes from the first configurations
in „Mischer SA612“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SA612A.pdf
tank oscillator suitable for output is connected to the internal positive supply by a 1.5k synthesizer-controlled applications. It is important to buffer the resistor. This permits direct output termination yet allows for output of this circuit to assure that switching spikes from the first balanced output
in „Colpitts Crystal Oscillator für 10MHz?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
trc101.pdf
enables the entire receiver chain when set. The receiver chain comprises the baseband circuit, synthesizer, and crystal oscillator. Bit [6] – Baseband Circuit Enable: This bit enables the baseband circuit when set. The baseband circuit, synthesizer, and oscillator work together to demodulate and recover
in „bidirektionale RS232 Funkbrücke mit RFM12“ · Projekte & Code ·
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Datei
rfm12.c
RF_SetRX() { disable_interrupts(GLOBAL); RF_Init_SPI(); RF_CMD(0x82C8); //Receiver Chain einschalten, Synth aus. RF_GetStatus(); // !!! Status holen, sonst klappt es nicht !!! EXT_INT_EDGE(1,H_TO_L); // INT1 fallende Flanke clear_interrupt(INT_EXT1); // Flag löschen RF_FIFO_State = 0; f_RX_FirstByte = 1;
in „PIC18: Getesteter CCS C-Code für RFM12 Modul“ · Projekte & Code ·
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Datei
synthesis.txt
<data_out>. Summary: inferred 32 Multiplexer(s). Unit <multiplexer4_1> synthesized. Synthesizing Unit <multiplexer2_1>. Related source file is "C:/Dokumente und Einstellungen/Harald/Desktop/Diplomarbeit/Code/Source/units/multiplexer2.vhd". Unit <multiplexer2_1> synthesized. Synthesizing
in „zu viele unconnected warnungen bei synthese“ · FPGA, VHDL & Co. ·
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Datei
DCM_versuch.vhd
xc5vlx50-ff676-1 -- -- Module DCM_versuch -- Generated by Xilinx Architecture Wizard -- Written for synthesis tool: XST library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity DCM_versuch is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic
in „DDR SDRAM Ansteuerung - Nutzung von XILINX MIG“ · FPGA, VHDL & Co. ·
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Datei
fifo.vhd
translate_on" specified -- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synopsys translate_off Library XilinxCoreLib; -- synopsys translate_on ENTITY fifo IS port
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Datei
Remote1.asm
temp1,0x82 ldi temp2,0b00111001 ;Empfänger aus,Basisband nicht blockiert,Sender an, rcall Send ;..Synthesizer an, Quartz an, Brownoutdetektor aus, ;..kein Wake-up des uC, Keine Clockausgabe ;3 Frequency-Setting (6h) ldi temp1,0b10100110 ;Offset: Ergibt Sendefrequenz (s. DB) ldi temp2,0b00100000 ;.. f=433,92MHz
in „Probleme mit SPI und RFM12“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Sender_und_Empf_nger.txt
Timer ;b2(eb): enable Low-Battery Detector ;b3(ex): Fährt den Oszillator hoch ;b4(es): Fährt den Synthesizer hoch ;b5(et): Schaltet den PLL + Ausgangsverstärker ein und beginnt ; mit dem Senden, falls das TX-Register aktiviert ist. ; et=1 --> alle anderen Bits sind für die Sendefunktion ; nicht mehr von
in „Funkmodul RFM12“ · Mikrocontroller und Digitale Elektronik ·
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PDF
S1D13305.pdf
flashing BL Error BL Error 0 1 0 0 Ruled line RL LINE RL LINE 0 1 LINE LINE 1 1 Figure 64. Layer synthesis A number of means can be used to achieve these effects, 16.5.2. Half-tone display depending on the display configuration. These are listed The FP parameter can be used to generate half-intensity
in „SP14Q002-A1 aus eBay - Erfahrungsaustausch“ · Mikrocontroller und Digitale Elektronik ·
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PDF
23861038920081.pdf
which should be read in conjunction with this data sheet. Features Applications Crystal controlled synthesiser for frequency accuracy Handheld Terminals Highly selective front -end, 175KHz improves range Environmental Sense & Control 10mW Transmit RF power output Vehicle to Base Station Data Transfer Serial
in „2 AVR`s per Funk vernetzen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
sed1330f.pdf
graphics Low power CMOS fabrication ...Up to 3 layers of graphics ....5mA (typical) Selectable display synthesis ....0.05 A (typical), standby ...Display attributes (reverse video, flashing, etc.) Single 5V supply for selected areas of the display Package...SED1330F BA QFP5-60pin (plastic) ...Simple animation
in „LCD Controller platine für SED1330F/SED1335F“ · Platinen ·
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PDF
MK715_Touchscreen.pdf
analogresistivetouchscreens.Italsoincludesageneral screen drive purpose A to D converter and a clock synthesizer. • Touch pressure can be measured • One or two general purpose A to D inputs The IC continually monitors the screen waiting for a touch. In this mode, the supply current is typically 4µA. • On-chip
in „Touchkontroller MK 715“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Spezifikation.pdf
Semiconductors 2 The I C-bus specification handbook, full pagewidth SDA SCL MICRO- CONTROLLER PCB83C528 PLL SYNTHESIZER TSA5512 NON-VOLATILE MEMORY PCF8582E M/S COLOUR DECODER TDA9160A STEREO / DUAL SOUND DECODER TDA9840 SDA SCL PICTURE DTMF SIGNAL GENERATOR IMPROVEMENT TDA4670 PCD3311 HI-FI LINE AUDIO INTERFACE
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PDF
ER400TRS.pdf
which should be read in conjunction with this data sheet. Features Applications Crystal controlled synthesiser for frequency accuracy Handheld Terminals Highly selective front-end, 175KHz improves range Environmental Sense & Control 10mW Transmit RF power output, -105dBm sensitivity Vehicle to Base Station
in „funkkomunikation zwischen 2 atmels?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
er400trs.pdf
which should be read in conjunction with this data sheet. Features Applications Crystal controlled synthesiser for frequency accuracy Handheld Terminals High sensitivity receiver – typically -105dBm @ 19.2 Kbps Environmental Sense & Control 10mW Transmit RF power output Vehicle to Base Station Data Transfer
in „Datenübertragung mittels ASK“ · Mikrocontroller und Digitale Elektronik ·
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PDF
data2bram.pdf
drf) files. • Produces .v (for Verilog) and .vhd (for VHDL) initialization files for pre- and post-synthesis simulation. • Seamlessly integrates initialization data into post-place and route simulations. • Produces Memory definition (.mem) files for Verilog simulations with third-party memory models. • Can
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PDF
ssfp16.pdf
Beschreibungen der untersten Ebene sind zum Teil speziell auf XILINX FPGAs zugeschnitten, da der Synthetisierer (zumindest ISE Webpack 8.1) leider bei Verhaltensbeschreibungen nicht immer optimale Ergebnisse liefert. 2.1.1 Register Es gibt 16 weitgehend gleichberechtigte 16-bit Register, r0 bis r15 benannt